diff options
| author | Henry Cook | 2015-08-12 19:32:43 -0700 |
|---|---|---|
| committer | Henry Cook | 2015-08-12 19:32:57 -0700 |
| commit | 85d7403f9bf7bc2b3520f924736c237f21f70ebd (patch) | |
| tree | 64560f779063a419395a2fb8a31ea52c52af4404 /src/test/scala/ChiselTests/RegisterVecShift.scala | |
| parent | 7e69966362b1dbd9835695250494857f3a3767c8 (diff) | |
being to convert tests to scala-test; tests compile and run
Diffstat (limited to 'src/test/scala/ChiselTests/RegisterVecShift.scala')
| -rw-r--r-- | src/test/scala/ChiselTests/RegisterVecShift.scala | 56 |
1 files changed, 0 insertions, 56 deletions
diff --git a/src/test/scala/ChiselTests/RegisterVecShift.scala b/src/test/scala/ChiselTests/RegisterVecShift.scala deleted file mode 100644 index ac2b0d59..00000000 --- a/src/test/scala/ChiselTests/RegisterVecShift.scala +++ /dev/null @@ -1,56 +0,0 @@ -package ChiselTests -import Chisel._ -import Chisel.testers._ - -class RegisterVecShift extends Module { - val io = new Bundle { - val ins = Vec(UInt(INPUT, 4), 4) - // val ins = Vec.fill(4){ UInt(INPUT, 4) } - val load = Bool(INPUT) - val shift = Bool(INPUT) - val out = UInt(OUTPUT, 4) - } - // val delays = Reg( init = Vec.fill(4){ UInt(0, 4) } ) - val delays = Reg( Vec(UInt(width = 4), 4) ) - when (reset) { - delays := Vec.fill(4){ UInt(0, 4) } - } - when (io.load) { - delays(0) := io.ins(0) - delays(1) := io.ins(1) - delays(2) := io.ins(2) - delays(3) := io.ins(3) - } .elsewhen(io.shift) { - delays(0) := io.ins(0) - delays(1) := delays(0) - delays(2) := delays(1) - delays(3) := delays(2) - } - io.out := delays(3) -} - - -class RegisterVecShiftTester(c: RegisterVecShift) extends Tester(c) { - val reg = Array.fill(4){ 0 } - val ins = Array.fill(4){ 0 } - for (t <- 0 until 16) { - for (i <- 0 until 4) - ins(i) = rnd.nextInt(16) - val shift = rnd.nextInt(2) - val load = rnd.nextInt(2) - for (i <- 0 until 4) - poke(c.io.ins(i), ins(i)) - poke(c.io.load, load) - poke(c.io.shift, shift) - step(1) - if (load == 1) { - for (i <- 0 until 4) - reg(i) = ins(i) - } else if (shift == 1) { - for (i <- 3 to 1 by -1) - reg(i) = reg(i-1) - reg(0) = ins(0) - } - expect(c.io.out, reg(3)) - } -} |
