diff options
| author | Jim Lawson | 2015-07-24 17:17:01 -0700 |
|---|---|---|
| committer | Jim Lawson | 2015-07-24 17:17:01 -0700 |
| commit | e73450165c59d68b524689a7169e03140a41a1c5 (patch) | |
| tree | b7236f80d9abf60775ecbcefe6f7ca25557dce73 /src/test/scala/ChiselTests/ModuleWire.scala | |
| parent | 94893bad972ded686a2c68dd334aa40b92e3b85d (diff) | |
| parent | 3976145bb8c7595ad0f0a7fbb4ccbbd3030d8873 (diff) | |
Merge pull request #1 from ucb-bar/packagedir
Packagedir
Diffstat (limited to 'src/test/scala/ChiselTests/ModuleWire.scala')
| -rw-r--r-- | src/test/scala/ChiselTests/ModuleWire.scala | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/src/test/scala/ChiselTests/ModuleWire.scala b/src/test/scala/ChiselTests/ModuleWire.scala new file mode 100644 index 00000000..13e74a06 --- /dev/null +++ b/src/test/scala/ChiselTests/ModuleWire.scala @@ -0,0 +1,30 @@ +package ChiselTests +import Chisel._ + +class Inc extends Module { + val io = new Bundle { + val in = UInt(INPUT, 32) + val out = UInt(OUTPUT, 32) + } + io.out := io.in + UInt(1) +} + +class ModuleWire extends Module { + val io = new Bundle { + val in = UInt(INPUT, 32) + val out = UInt(OUTPUT, 32) + } + val inc = Module(new Inc).io + inc.in := io.in + io.out := inc.out +} + + +class ModuleWireTester(c: ModuleWire) extends Tester(c) { + for (t <- 0 until 16) { + val test_in = rnd.nextInt(256) + poke(c.io.in, test_in) + step(1) + expect(c.io.out, test_in + 1) + } +} |
