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authorHenry Cook2015-08-12 19:32:43 -0700
committerHenry Cook2015-08-12 19:32:57 -0700
commit85d7403f9bf7bc2b3520f924736c237f21f70ebd (patch)
tree64560f779063a419395a2fb8a31ea52c52af4404 /src/test/scala/ChiselTests/EnableShiftRegister.scala
parent7e69966362b1dbd9835695250494857f3a3767c8 (diff)
being to convert tests to scala-test; tests compile and run
Diffstat (limited to 'src/test/scala/ChiselTests/EnableShiftRegister.scala')
-rw-r--r--src/test/scala/ChiselTests/EnableShiftRegister.scala40
1 files changed, 0 insertions, 40 deletions
diff --git a/src/test/scala/ChiselTests/EnableShiftRegister.scala b/src/test/scala/ChiselTests/EnableShiftRegister.scala
deleted file mode 100644
index a0b2e88d..00000000
--- a/src/test/scala/ChiselTests/EnableShiftRegister.scala
+++ /dev/null
@@ -1,40 +0,0 @@
-package ChiselTests
-import Chisel._
-import Chisel.testers._
-
-class EnableShiftRegister extends Module {
- val io = new Bundle {
- val in = UInt(INPUT, 4)
- val shift = Bool(INPUT)
- val out = UInt(OUTPUT, 4)
- }
- val r0 = Reg(init = UInt(0, 4))
- val r1 = Reg(init = UInt(0, 4))
- val r2 = Reg(init = UInt(0, 4))
- val r3 = Reg(init = UInt(0, 4))
- when(io.shift) {
- r0 := io.in
- r1 := r0
- r2 := r1
- r3 := r2
- }
- io.out := r3
-}
-
-class EnableShiftRegisterTester(c: EnableShiftRegister) extends Tester(c) {
- val reg = Array.fill(4){ 0 }
- for (t <- 0 until 16) {
- val in = rnd.nextInt(16)
- val shift = rnd.nextInt(2)
- println("SHIFT " + shift + " IN " + in)
- poke(c.io.in, in)
- poke(c.io.shift, shift)
- step(1)
- if (shift == 1) {
- for (i <- 3 to 1 by -1)
- reg(i) = reg(i-1)
- reg(0) = in
- }
- expect(c.io.out, reg(3))
- }
-}