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| author | Andrew Waterman | 2015-08-02 15:29:53 -0700 |
|---|---|---|
| committer | Andrew Waterman | 2015-08-02 15:30:25 -0700 |
| commit | 9938d33ef381c4931b2a94cde0cae2bcb1ed9160 (patch) | |
| tree | 3fe57d3549c8fb04a713b5654a8b527a56d2e578 /src/test/scala/ChiselTests/ComplexAssign.scala | |
| parent | 2a34ac4a4196c04dfdbc9be73833896e693ff96e (diff) | |
Work around FIRRTL initialization pedantry
Initialize all wires, output ports, and instance input ports to 0.
Diffstat (limited to 'src/test/scala/ChiselTests/ComplexAssign.scala')
0 files changed, 0 insertions, 0 deletions