Rewrite BlackBox IO contract, replace _clock|_reset

The old blackbox behavior still emitted extmodules that have a
clk, reset pin and prepended all io's with io_ (ultimately). Most
verilog modules do not follow this distinction (or use a slightly
different name for clock and so on).

Thus, instead BlackBox has been rewritten to not assume a clk or
reset pin. Instead, the io Bundle specified is flattened directly
into the Module.ports declaration. The tests have been rewritten
to compensate for this. Also, added a test that uses the clock pin.

As a secondary change, the _clock and _reset module parameters were
bad for two reasons. One, they used null as a default, which is a
scala best practices violation. Two, they were just not good names.

Instead the primary constructor has been rewritten to take an
Option[Clock] called override_clock and an Option[Bool] called
override_reset, which default to None. (Note how the getOrElse call
down below is much more natural now.)

However, users may not want to specify the Some(their_clock) so I
also added secondary constructors that take parameters named clock
and reset and wrap them into Some calls into the primary constructor.
This is a better UX because now you can just stipulate clock=blah in
instantiation of that module in symmetry with using the clock in the
definition of the module by invoking clock.

PS: We could also back out of allowing any overrides via the Module
constructor and just require the instantiating Module to do
submodule.clock := newclock, etc.

1 files changed, 27 insertions, 10 deletions

diff --git a/src/test/resources/BlackBoxTest.v b/src/test/resources/BlackBoxTest.v
index e57d2852..910b09ff 100644
--- a/src/test/resources/BlackBoxTest.v
+++ b/src/test/resources/BlackBoxTest.v
@@ -1,17 +1,34 @@
 module BlackBoxInverter(
-    input  [0:0] clk,
-    input  [0:0] reset,
-    output [0:0] io_in,
-    output [0:0] io_out
+    input  [0:0] in,
+    output [0:0] out
 );
-  assign io_out = !io_in;
+  assign out = !in;
 endmodule
 
 module BlackBoxPassthrough(
-    input  [0:0] clk,
-    input  [0:0] reset,
-    output [0:0] io_in,
-    output [0:0] io_out
+    input  [0:0] in,
+    output [0:0] out
 );
-  assign io_out = io_in;
+  assign out = in;
+endmodule
+
+module BlackBoxRegister(
+    input  [0:0] clock,
+    input  [0:0] in,
+    output [0:0] out
+);
+  reg [0:0] register;
+  always @(posedge clock) begin
+    register <= in;
+  end
+  assign out = register;
+endmodule
+
+module BlackBoxConstant #(
+  parameter int WIDTH=1,
+  parameter int VALUE=1
+) (
+  output [WIDTH-1:0] out
+);
+  assign out = VALUE;
 endmodule