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authorJim Lawson2017-05-11 15:07:30 -0700
committerGitHub2017-05-11 15:07:30 -0700
commit8baa2ab806be1aa85a7a1da7b348726da1bd1d19 (patch)
tree9c6251d52cb17830a9ce212c7630bf0d9fecf002 /src/test/resources/chisel3/VerilogVendingMachine.v
parent45e235a5948a1cd15b8ccb5f437dc6f2ff80cb96 (diff)
Scope resources - move them down into chisel3 directory - fixes #549 (#610)
Diffstat (limited to 'src/test/resources/chisel3/VerilogVendingMachine.v')
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diff --git a/src/test/resources/chisel3/VerilogVendingMachine.v b/src/test/resources/chisel3/VerilogVendingMachine.v
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+// See LICENSE for license details.
+
+// A simple Verilog FSM vending machine implementation
+module VerilogVendingMachine(
+ input clock,
+ input reset,
+ input nickel,
+ input dime,
+ output dispense
+);
+ parameter sIdle = 3'd0, s5 = 3'd1, s10 = 3'd2, s15 = 3'd3, sOk = 3'd4;
+ reg [2:0] state;
+ wire [2:0] next_state;
+
+ assign dispense = (state == sOk) ? 1'd1 : 1'd0;
+
+ always @(*) begin
+ case (state)
+ sIdle: if (nickel) next_state <= s5;
+ else if (dime) next_state <= s10;
+ else next_state <= state;
+ s5: if (nickel) next_state <= s10;
+ else if (dime) next_state <= s15;
+ else next_state <= state;
+ s10: if (nickel) next_state <= s15;
+ else if (dime) next_state <= sOk;
+ else next_state <= state;
+ s15: if (nickel) next_state <= sOk;
+ else if (dime) next_state <= sOk;
+ else next_state <= state;
+ sOk: next_state <= sIdle;
+ endcase
+ end
+
+ // Go to next state
+ always @(posedge clock) begin
+ if (reset) begin
+ state <= sIdle;
+ end else begin
+ state <= next_state;
+ end
+ end
+endmodule
+