summaryrefslogtreecommitdiff
path: root/src/main
diff options
context:
space:
mode:
authorJim Lawson2016-09-29 11:44:09 -0700
committerJim Lawson2016-09-29 11:44:09 -0700
commiteb5e5dc30019be342b7a0534b425bf33b7984ce3 (patch)
tree1f04fd7157a17cc45fe1ff0835500d93809809fd /src/main
parent12a651513541d6c96e3b709b424d5d3384179076 (diff)
Massive rename of CompileOptions.
Massage CompileOption names in an attempt to preserve default (Strict) CompileOptions in the absence of explicit imports. NOTE: Since the default is now strict, we may encounter errors when we generate connections for clients (i.e., in Vec.do_apply() when we wire up a sequence). We should really thread the CompileOptions through the macro system so the client's implicits are used.
Diffstat (limited to 'src/main')
-rw-r--r--src/main/scala/chisel3/compatibility.scala2
-rw-r--r--src/main/scala/chisel3/testers/BasicTester.scala2
-rw-r--r--src/main/scala/chisel3/util/Arbiter.scala2
-rw-r--r--src/main/scala/chisel3/util/Counter.scala2
-rw-r--r--src/main/scala/chisel3/util/Decoupled.scala2
-rw-r--r--src/main/scala/chisel3/util/LFSR.scala2
-rw-r--r--src/main/scala/chisel3/util/Reg.scala2
-rw-r--r--src/main/scala/chisel3/util/Valid.scala2
8 files changed, 8 insertions, 8 deletions
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 3b1b5b0a..646fc84e 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -4,7 +4,7 @@
// moving to the more standard package naming convention chisel3 (lowercase c).
package object Chisel { // scalastyle:ignore package.object.name
- implicit val defaultCompileOptions = chisel3.NotStrict.CompileOptions
+ implicit val defaultCompileOptions = chisel3.ExplicitCompileOptions.NotStrict
type Direction = chisel3.core.Direction
val INPUT = chisel3.core.Direction.Input
val OUTPUT = chisel3.core.Direction.Output
diff --git a/src/main/scala/chisel3/testers/BasicTester.scala b/src/main/scala/chisel3/testers/BasicTester.scala
index edb32853..93bb4c33 100644
--- a/src/main/scala/chisel3/testers/BasicTester.scala
+++ b/src/main/scala/chisel3/testers/BasicTester.scala
@@ -9,7 +9,7 @@ import internal._
import internal.Builder.pushCommand
import internal.firrtl._
import internal.sourceinfo.SourceInfo
-import chisel3.NotStrict.CompileOptions
+//import chisel3.ExplicitCompileOptions.NotStrict
class BasicTester extends Module() {
// The testbench has no IOs, rather it should communicate using printf, assert, and stop.
diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala
index 67e28617..adeb1b34 100644
--- a/src/main/scala/chisel3/util/Arbiter.scala
+++ b/src/main/scala/chisel3/util/Arbiter.scala
@@ -6,7 +6,7 @@
package chisel3.util
import chisel3._
-import chisel3.NotStrict.CompileOptions
+//import chisel3.ExplicitCompileOptions.NotStrict
/** IO bundle definition for an Arbiter, which takes some number of ready-valid inputs and outputs
* (selects) at most one.
diff --git a/src/main/scala/chisel3/util/Counter.scala b/src/main/scala/chisel3/util/Counter.scala
index 5d9b8c3c..b22cfa7b 100644
--- a/src/main/scala/chisel3/util/Counter.scala
+++ b/src/main/scala/chisel3/util/Counter.scala
@@ -3,7 +3,7 @@
package chisel3.util
import chisel3._
-import chisel3.Strict.CompileOptions
+//import chisel3.ExplicitCompileOptions.Strict
/** A counter module
*
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 70b191bd..947d02f8 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -6,7 +6,7 @@
package chisel3.util
import chisel3._
-import chisel3.NotStrict.CompileOptions
+//import chisel3.ExplicitCompileOptions.NotStrict
/** An I/O Bundle containing 'valid' and 'ready' signals that handshake
* the transfer of data stored in the 'bits' subfield.
diff --git a/src/main/scala/chisel3/util/LFSR.scala b/src/main/scala/chisel3/util/LFSR.scala
index e3c29e79..95b4da81 100644
--- a/src/main/scala/chisel3/util/LFSR.scala
+++ b/src/main/scala/chisel3/util/LFSR.scala
@@ -6,7 +6,7 @@
package chisel3.util
import chisel3._
-import chisel3.Strict.CompileOptions
+//import chisel3.ExplicitCompileOptions.Strict
// scalastyle:off magic.number
object LFSR16 {
diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala
index 307812f8..fcfc9ac5 100644
--- a/src/main/scala/chisel3/util/Reg.scala
+++ b/src/main/scala/chisel3/util/Reg.scala
@@ -3,7 +3,7 @@
package chisel3.util
import chisel3._
-import chisel3.NotStrict.CompileOptions
+//import chisel3.ExplicitCompileOptions.NotStrict
object RegNext {
/** Returns a register with the specified next and no reset initialization.
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index ed4c3721..67be7648 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -6,7 +6,7 @@
package chisel3.util
import chisel3._
-import chisel3.NotStrict.CompileOptions
+//import chisel3.ExplicitCompileOptions.NotStrict
/** An Bundle containing data and a signal determining if it is valid */
class Valid[+T <: Data](gen: T) extends Bundle