Use a PhaseManager for Driver internals

Migrate Driver to use a PhaseManager to internally resolve Phase
ordering. This requires the use of an identity node to adequately
describe the necessary prerequisite/dependents.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

2 files changed, 67 insertions, 24 deletions

diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index 66146755..a78cc92f 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -6,7 +6,8 @@ import chisel3.internal.ErrorLog
 import chisel3.experimental.RawModule
 import internal.firrtl._
 import firrtl._
-import firrtl.options.Phase
+import firrtl.options.{Phase, PhaseManager}
+import firrtl.options.phases.DeletedWrapper
 import firrtl.options.Viewer.view
 import firrtl.annotations.JsonProtocol
 import firrtl.util.{BackendCompilationUtilities => FirrtlBackendCompilationUtilities}
@@ -200,22 +201,27 @@ object Driver extends BackendCompilationUtilities {
       optionsManager: ExecutionOptionsManager with HasChiselExecutionOptions with HasFirrtlOptions,
       dut: () => RawModule): ChiselExecutionResult = {
 
-    val annos = ChiselGeneratorAnnotation(dut) +:
-      (optionsManager.chiselOptions.toAnnotations ++
-         optionsManager.firrtlOptions.toAnnotations ++
-         optionsManager.commonOptions.toAnnotations)
+    val annos: AnnotationSeq =
+      Seq(DriverCompatibility.OptionsManagerAnnotation(optionsManager), ChiselGeneratorAnnotation(dut)) ++
+        optionsManager.chiselOptions.toAnnotations ++
+        optionsManager.firrtlOptions.toAnnotations ++
+        optionsManager.commonOptions.toAnnotations
 
-    val phases: Seq[Phase] =
-      Seq( new DriverCompatibility.AddImplicitOutputFile,
-           new DriverCompatibility.AddImplicitOutputAnnotationFile,
-           new DriverCompatibility.DisableFirrtlStage,
-           new ChiselStage,
-           new DriverCompatibility.MutateOptionsManager(optionsManager),
-           new DriverCompatibility.ReEnableFirrtlStage,
-           new firrtl.stage.phases.DriverCompatibility.AddImplicitOutputFile,
-           new firrtl.stage.phases.DriverCompatibility.AddImplicitEmitter,
-           new chisel3.stage.phases.MaybeFirrtlStage )
-        .map(firrtl.options.phases.DeletedWrapper(_))
+    val targets =
+      Seq( classOf[DriverCompatibility.AddImplicitOutputFile],
+           classOf[DriverCompatibility.AddImplicitOutputAnnotationFile],
+           classOf[DriverCompatibility.DisableFirrtlStage],
+           classOf[ChiselStage],
+           classOf[DriverCompatibility.MutateOptionsManager],
+           classOf[DriverCompatibility.ReEnableFirrtlStage],
+           classOf[DriverCompatibility.FirrtlPreprocessing],
+           classOf[chisel3.stage.phases.MaybeFirrtlStage] )
+    val currentState =
+      Seq( classOf[firrtl.stage.phases.DriverCompatibility.AddImplicitFirrtlFile] )
+
+    val phases: Seq[Phase] = new PhaseManager(targets, currentState) {
+      override val wrappers = Seq( DeletedWrapper(_: Phase) )
+    }.transformOrder
 
     val annosx = try {
       phases.foldLeft(annos)( (a, p) => p.transform(a) )
diff --git a/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala b/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala
index 0af796a4..11264ece 100644
--- a/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala
+++ b/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala
@@ -4,12 +4,12 @@ package chisel3.stage.phases
 
 import firrtl.{AnnotationSeq, ExecutionOptionsManager, HasFirrtlOptions}
 import firrtl.annotations.NoTargetAnnotation
-import firrtl.options.{OutputAnnotationFileAnnotation, Phase, PreservesAll}
+import firrtl.options.{OptionsException, OutputAnnotationFileAnnotation, Phase, PreservesAll, Unserializable}
 import firrtl.stage.{FirrtlCircuitAnnotation, RunFirrtlTransformAnnotation}
 import firrtl.stage.phases.DriverCompatibility.TopNameAnnotation
 
 import chisel3.HasChiselExecutionOptions
-import chisel3.stage.{NoRunFirrtlCompilerAnnotation, ChiselOutputFileAnnotation}
+import chisel3.stage.{ChiselStage, NoRunFirrtlCompilerAnnotation, ChiselOutputFileAnnotation}
 
 /** This provides components of a compatibility wrapper around Chisel's deprecated [[chisel3.Driver]].
   *
@@ -25,9 +25,9 @@ object DriverCompatibility {
     * the correct behavior before a circuit has been elaborated.
     * @note the output suffix is unspecified and will be set by the underlying [[firrtl.EmittedComponent]]
     */
-private [chisel3] class AddImplicitOutputFile extends Phase with PreservesAll[Phase] {
+  private [chisel3] class AddImplicitOutputFile extends Phase with PreservesAll[Phase] {
 
-    override val dependents = Seq( classOf[firrtl.stage.phases.DriverCompatibility.AddImplicitOutputFile] )
+    override val dependents = Seq(classOf[chisel3.stage.ChiselStage])
 
     def transform(annotations: AnnotationSeq): AnnotationSeq = {
       val hasOutputFile = annotations
@@ -51,6 +51,8 @@ private [chisel3] class AddImplicitOutputFile extends Phase with PreservesAll[Ph
     */
   private[chisel3] class AddImplicitOutputAnnotationFile extends Phase with PreservesAll[Phase] {
 
+    override val dependents = Seq(classOf[chisel3.stage.ChiselStage])
+
     def transform(annotations: AnnotationSeq): AnnotationSeq =
       annotations
         .collectFirst{ case _: OutputAnnotationFileAnnotation => annotations }
@@ -71,14 +73,18 @@ private [chisel3] class AddImplicitOutputFile extends Phase with PreservesAll[Ph
     * situations where you need to do something between Chisel compilation and FIRRTL compilations, e.g., update a
     * mutable data structure.
     */
-  private[chisel3] class DisableFirrtlStage extends Phase {
+  private[chisel3] class DisableFirrtlStage extends Phase with PreservesAll[Phase] {
+
+    override val dependents = Seq(classOf[ChiselStage])
 
     def transform(annotations: AnnotationSeq): AnnotationSeq = annotations
       .collectFirst { case NoRunFirrtlCompilerAnnotation => annotations                              }
       .getOrElse    { Seq(RunFirrtlCompilerAnnotation, NoRunFirrtlCompilerAnnotation) ++ annotations }
   }
 
-  private[chisel3] class ReEnableFirrtlStage extends Phase {
+  private[chisel3] class ReEnableFirrtlStage extends Phase with PreservesAll[Phase] {
+
+    override val prerequisites = Seq(classOf[DisableFirrtlStage], classOf[ChiselStage])
 
     def transform(annotations: AnnotationSeq): AnnotationSeq = annotations
       .collectFirst { case RunFirrtlCompilerAnnotation =>
@@ -92,15 +98,27 @@ private [chisel3] class AddImplicitOutputFile extends Phase with PreservesAll[Ph
 
   }
 
+  private[chisel3] case class OptionsManagerAnnotation(
+    manager: ExecutionOptionsManager with HasChiselExecutionOptions with HasFirrtlOptions)
+      extends NoTargetAnnotation with Unserializable
+
   /** Mutate an input [[firrtl.ExecutionOptionsManager]] based on information encoded in an [[firrtl.AnnotationSeq]].
     * This is intended to be run between [[chisel3.stage.ChiselStage ChiselStage]] and [[firrtl.stage.FirrtlStage]] if
     * you want to have backwards compatibility with an [[firrtl.ExecutionOptionsManager]].
     */
-  private[chisel3] class MutateOptionsManager(
-    optionsManager: ExecutionOptionsManager with HasChiselExecutionOptions with HasFirrtlOptions) extends Phase {
+  private[chisel3] class MutateOptionsManager extends Phase with PreservesAll[Phase] {
+
+    override val prerequisites = Seq(classOf[chisel3.stage.ChiselStage])
+
+    override val dependents = Seq(classOf[ReEnableFirrtlStage])
 
     def transform(annotations: AnnotationSeq): AnnotationSeq = {
 
+      val optionsManager = annotations
+        .collectFirst{ case OptionsManagerAnnotation(a) => a }
+        .getOrElse{ throw new OptionsException(
+                     "An OptionsManagerException must exist for Chisel Driver compatibility mode") }
+
       val firrtlCircuit = annotations.collectFirst{ case FirrtlCircuitAnnotation(a) => a }
       optionsManager.firrtlOptions = optionsManager.firrtlOptions.copy(
         firrtlCircuit = firrtlCircuit,
@@ -114,4 +132,23 @@ private [chisel3] class AddImplicitOutputFile extends Phase with PreservesAll[Ph
 
   }
 
+  /** A [[Phase]] that lets us run
+    * @todo a better solution than the current state hack below may be needed
+    */
+  private [chisel3] class FirrtlPreprocessing extends Phase with PreservesAll[Phase] {
+
+    override val prerequisites = Seq(classOf[ChiselStage], classOf[MutateOptionsManager], classOf[ReEnableFirrtlStage])
+
+    override val dependents = Seq(classOf[MaybeFirrtlStage])
+
+    private val phases =
+      Seq( new firrtl.stage.phases.DriverCompatibility.AddImplicitOutputFile,
+           new firrtl.stage.phases.DriverCompatibility.AddImplicitEmitter )
+
+    override def transform(annotations: AnnotationSeq): AnnotationSeq =
+      phases
+        .foldLeft(annotations)( (a, p) => p.transform(a) )
+
+  }
+
 }