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| author | Jim Lawson | 2020-01-07 14:35:18 -0800 |
|---|---|---|
| committer | GitHub | 2020-01-07 14:35:18 -0800 |
| commit | c4aa70f64ad5ecd8a5557ad0e4777f245768d865 (patch) | |
| tree | a447f56b55065bdc2f4e05e0195f050e2cb431db /src/main | |
| parent | 2224274cc5a42caa1e74b45573b4c7c09c85d227 (diff) | |
| parent | d4300b9deae6dde7ce0f314ea73a9ca4a1c3868c (diff) | |
Merge branch 'master' into add-asbool-to-clock
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/chisel3/stage/package.scala | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/stage/package.scala b/src/main/scala/chisel3/stage/package.scala index 67d38ae7..57766be6 100644 --- a/src/main/scala/chisel3/stage/package.scala +++ b/src/main/scala/chisel3/stage/package.scala @@ -28,7 +28,6 @@ package object stage { private[chisel3] implicit object ChiselExecutionResultView extends OptionsView[ChiselExecutionResult] { - lazy val dummyWriteEmitted = new firrtl.stage.phases.WriteEmitted lazy val dummyConvert = new Convert lazy val dummyEmitter = new Emitter |