diff options
| author | Andrew Waterman | 2015-07-31 16:46:40 -0700 |
|---|---|---|
| committer | Andrew Waterman | 2015-07-31 16:47:17 -0700 |
| commit | b08d9a2946cc27a360dabab3089095ea46786524 (patch) | |
| tree | 850e00f311655044c03ced05858a968cf5721e26 /src/main | |
| parent | d5c668d96f5137b2f35e19eb5f13294aaf19b08d (diff) | |
Disallow dynamic bit range extraction
It wasn't correctly implemented, anyway.
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/Chisel/Core.scala | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala index 2e8feabc..f4a53d41 100644 --- a/src/main/scala/Chisel/Core.scala +++ b/src/main/scala/Chisel/Core.scala @@ -615,8 +615,6 @@ sealed abstract class Bits(dirArg: Direction, width: Int, lit: Option[LitArg]) e } final def apply(x: Int, y: Int): UInt = apply(BigInt(x), BigInt(y)) - final def apply(x: UInt, y: UInt): UInt = - apply(x.litValue(), y.litValue()) protected[Chisel] def unop(op: PrimOp, width: Int): this.type = { val d = cloneTypeWidth(width) |