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authorSchuyler Eldridge2019-08-14 16:15:05 -0400
committerSchuyler Eldridge2019-08-27 19:18:32 -0400
commitb060168ec05689e4a8ccf790c0770bd2c4376194 (patch)
tree1d956a318f6e7999df8b4efabec286f8aca79c18 /src/main
parent4531394fb54746cca62c7be7251bc24c8f077d6c (diff)
Remove stack trace trimming in Elaborate phase
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/main')
-rw-r--r--src/main/scala/chisel3/stage/phases/Elaborate.scala23
1 files changed, 2 insertions, 21 deletions
diff --git a/src/main/scala/chisel3/stage/phases/Elaborate.scala b/src/main/scala/chisel3/stage/phases/Elaborate.scala
index 150eacbe..0f92c480 100644
--- a/src/main/scala/chisel3/stage/phases/Elaborate.scala
+++ b/src/main/scala/chisel3/stage/phases/Elaborate.scala
@@ -15,28 +15,9 @@ import firrtl.options.{OptionsException, Phase, PreservesAll}
*/
class Elaborate extends Phase with PreservesAll[Phase] {
- /**
- * @todo Change this to print to STDERR (`Console.err.println`)
- */
def transform(annotations: AnnotationSeq): AnnotationSeq = annotations.flatMap {
- case a: ChiselGeneratorAnnotation =>
- try {
- a.elaborate
- } catch {
- case e: OptionsException => throw e
- case e: ChiselException =>
- val copts = view[ChiselOptions](annotations)
- val stackTrace = if (!copts.printFullStackTrace) {
- e.chiselStackTrace
- } else {
- val s = new StringWriter
- e.printStackTrace(new PrintWriter(s))
- s.toString
- }
- Predef.augmentString(stackTrace).lines.foreach(line => println(s"${ErrorLog.errTag} $line"))
- Some(a)
- }
- case a => Some(a)
+ case a: ChiselGeneratorAnnotation => a.elaborate
+ case a => Some(a)
}
}