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authormergify[bot]2022-06-01 20:32:31 +0000
committerGitHub2022-06-01 20:32:31 +0000
commit97fde23f666a560d4eba9333e4230f901d7f5361 (patch)
treeb8434cba3666491dc59aa323dce399e77cb7a576 /src/main
parent0c811b490f47f20f2e81c58706924e56611b6ba2 (diff)
Add formatted Printable interpolator `cf` (#2528) (#2553)
This is a formatted version of the p"..." interpolator analogous to Scala's f"..." interpolator. The primary difference is that it supports formatting interpolated variables by following the variable with "%<specifier>". For example: printf(cf"myWire = $myWire%x\n") This will format the hardware value "myWire" as a hexidecimal value in the emitted Verilog. Note that literal "%" must be escaped as "%%". Scala types and format specifiers are supported and are handled in the same manner as in standard Scala f"..." interpolators. (cherry picked from commit 037f7b2ff3a46184d1b82e1b590a7572bfa6a76b) Co-authored-by: Girish Pai <girish.pai@sifive.com>
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