diff options
| author | jackkoenig | 2016-03-18 01:02:56 -0700 |
|---|---|---|
| committer | jackkoenig | 2016-03-18 01:02:56 -0700 |
| commit | 8e15bd90e179be15145ca3b04b8a4498fc0a9b73 (patch) | |
| tree | a3c3a07c358a2e595ea29ebf6aca478ee9bc1f20 /src/main | |
| parent | e6ee1ddb79c219e313e530a029d8402274fbaebc (diff) | |
Only randomize directory names during testing
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/Chisel/testers/TesterDriver.scala | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/src/main/scala/Chisel/testers/TesterDriver.scala b/src/main/scala/Chisel/testers/TesterDriver.scala index 4547f48f..c0cdfb3f 100644 --- a/src/main/scala/Chisel/testers/TesterDriver.scala +++ b/src/main/scala/Chisel/testers/TesterDriver.scala @@ -30,8 +30,7 @@ object TesterDriver extends BackendCompilationUtilities { val target = circuit.name val path = createTempDirectory(target) - val fname = File.createTempFile(target, "", path) - val prefix = fname.toString.split("/").last + val fname = new File(path, target) // For now, dump the IR out to a file Driver.dumpFirrtl(circuit, Some(new File(fname.toString + ".fir"))) @@ -47,10 +46,10 @@ object TesterDriver extends BackendCompilationUtilities { }) // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe - if ((firrtlToVerilog(prefix, path) #&& - verilogToCpp(prefix, path, additionalVFiles, cppHarness) #&& - cppToExe(prefix, path)).! == 0) { - executeExpectingSuccess(prefix, path) + if ((firrtlToVerilog(target, path) #&& + verilogToCpp(target, path, additionalVFiles, cppHarness) #&& + cppToExe(target, path)).! == 0) { + executeExpectingSuccess(target, path) } else { false } |
