diff options
| author | Schuyler Eldridge | 2020-03-26 16:27:24 -0400 |
|---|---|---|
| committer | GitHub | 2020-03-26 13:27:24 -0700 |
| commit | 81845909248aaceef427e73924211931e0dc60dc (patch) | |
| tree | 3789f0825eb2cca8c18389b39893b76b70f3371a /src/main | |
| parent | dbb024a9adee6d82f37e357cf8b55456674ff65c (diff) | |
Set StageError cause in ChiselStage (#1382)
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/chisel3/stage/ChiselStage.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/stage/ChiselStage.scala b/src/main/scala/chisel3/stage/ChiselStage.scala index ea40e92b..0068d86f 100644 --- a/src/main/scala/chisel3/stage/ChiselStage.scala +++ b/src/main/scala/chisel3/stage/ChiselStage.scala @@ -46,7 +46,7 @@ class ChiselStage extends Stage with PreservesAll[Phase] { .augmentString(stackTrace) .lines .foreach(line => println(s"${ErrorLog.errTag} $line")) // scalastyle:ignore regex - throw new StageError() + throw new StageError(cause=ce) } /** Convert a Chisel module to a CHIRRTL string |