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authorJim Lawson2020-01-21 14:37:40 -0800
committerGitHub2020-01-21 14:37:40 -0800
commit76c986ebb2107c9872479d478d0e269ad5e5b08a (patch)
treedbfabb158592e44028ebecf9610e1fa896c9a497 /src/main
parentce82ffaaeb2301af756b032c01e879e700299ea1 (diff)
parentc7715c160a0dd07765e736b813c8b6b26b27de28 (diff)
Merge branch 'master' into fix-bitpat-whitespace
Diffstat (limited to 'src/main')
-rw-r--r--src/main/scala/chisel3/aop/Select.scala7
-rw-r--r--src/main/scala/chisel3/stage/ChiselStage.scala2
2 files changed, 6 insertions, 3 deletions
diff --git a/src/main/scala/chisel3/aop/Select.scala b/src/main/scala/chisel3/aop/Select.scala
index 612cdcc7..390f82a5 100644
--- a/src/main/scala/chisel3/aop/Select.scala
+++ b/src/main/scala/chisel3/aop/Select.scala
@@ -80,8 +80,11 @@ object Select {
*/
def instances(module: BaseModule): Seq[BaseModule] = {
check(module)
- module._component.get.asInstanceOf[DefModule].commands.collect {
- case i: DefInstance => i.id
+ module._component.get match {
+ case d: DefModule => d.commands.collect {
+ case i: DefInstance => i.id
+ }
+ case other => Nil
}
}
diff --git a/src/main/scala/chisel3/stage/ChiselStage.scala b/src/main/scala/chisel3/stage/ChiselStage.scala
index 0a0cc47c..df23f97d 100644
--- a/src/main/scala/chisel3/stage/ChiselStage.scala
+++ b/src/main/scala/chisel3/stage/ChiselStage.scala
@@ -16,7 +16,7 @@ import java.io.{StringWriter, PrintWriter}
class ChiselStage extends Stage with PreservesAll[Phase] {
val shell: Shell = new Shell("chisel") with ChiselCli with FirrtlCli
- val targets =
+ val targets: Seq[PhaseManager.PhaseDependency] =
Seq( classOf[chisel3.stage.phases.Checks],
classOf[chisel3.stage.phases.Elaborate],
classOf[chisel3.stage.phases.AddImplicitOutputFile],