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authorJiuyang Liu2021-11-16 04:20:50 +0800
committerGitHub2021-11-16 04:20:50 +0800
commit670c539110a599642d700323a34159be0f5abb12 (patch)
tree79a969333c9af8fdd3208890bf4a419f4fc3b6d5 /src/main
parent4606b30b02284ab82dd46f2345ecb96c39e57c99 (diff)
parent8c24afd170bdc32e8220f493fc7c64b5e7bd01e8 (diff)
Merge pull request #2170 from chipsalliance/remove_toBools
Remove toBools
Diffstat (limited to 'src/main')
-rw-r--r--src/main/scala/chisel3/compatibility.scala1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index ffbb7e27..d1e7b4f1 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -637,6 +637,7 @@ package object Chisel {
final def toUInt(implicit compileOptions: CompileOptions): UInt = a.do_asUInt(DeprecatedSourceInfo, compileOptions)
+ final def toBools(implicit compileOptions: CompileOptions): Seq[Bool] = a.do_asBools(DeprecatedSourceInfo, compileOptions)
}
}