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authorSchuyler Eldridge2019-10-21 14:56:26 -0400
committerGitHub2019-10-21 14:56:26 -0400
commit66f5696e03a529ced36504e53f7b2fc24d31544c (patch)
treee8208ae30e34131e8c2722784cb62a6c8300fe43 /src/main
parent7b93b0f8c48e39cc9730cf9f91340cf733dadafe (diff)
parent22434659d8ac8a7855c7d7c00c7adf71e8e1099b (diff)
Merge pull request #1175 from freechipsproject/bore-name
Internal BoringUtils.bore Bug Fix
Diffstat (limited to 'src/main')
-rw-r--r--src/main/scala/chisel3/util/experimental/BoringUtils.scala8
1 files changed, 7 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/util/experimental/BoringUtils.scala b/src/main/scala/chisel3/util/experimental/BoringUtils.scala
index da5b3fd0..36b3fb88 100644
--- a/src/main/scala/chisel3/util/experimental/BoringUtils.scala
+++ b/src/main/scala/chisel3/util/experimental/BoringUtils.scala
@@ -181,8 +181,14 @@ object BoringUtils {
* component
*/
def bore(source: Data, sinks: Seq[Data]): String = {
- lazy val genName = addSource(source, source.instanceName, true, true)
+ val boringName = try {
+ source.instanceName
+ } catch {
+ case _: Exception => "bore"
+ }
+ val genName = addSource(source, boringName, true, true)
sinks.map(addSink(_, genName, true, true))
genName
}
+
}