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authorDeborah Soung2021-07-06 14:40:59 -0700
committerGitHub2021-07-06 14:40:59 -0700
commit503ae520e7f997bcbc639b79869c9a4214d402ed (patch)
tree7e72d44b7e023fac04fdbe8d95d5bfdc01001988 /src/main
parent4b7499f7c6287c696111bd7c6ee060f33f667419 (diff)
Make printf return BaseSim subclass so it can be named/annotated (#1992)
Diffstat (limited to 'src/main')
-rw-r--r--src/main/scala/chisel3/aop/Select.scala4
-rw-r--r--src/main/scala/chisel3/internal/firrtl/Emitter.scala4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/main/scala/chisel3/aop/Select.scala b/src/main/scala/chisel3/aop/Select.scala
index a16c415c..078422bb 100644
--- a/src/main/scala/chisel3/aop/Select.scala
+++ b/src/main/scala/chisel3/aop/Select.scala
@@ -281,7 +281,7 @@ object Select {
val printfs = mutable.ArrayBuffer[Printf]()
searchWhens(module, (cmd: Command, preds: Seq[Predicate]) => {
cmd match {
- case chisel3.internal.firrtl.Printf(_, clock, pable) => printfs += Printf(preds, pable, getId(clock).asInstanceOf[Clock])
+ case chisel3.internal.firrtl.Printf(id, _, clock, pable) => printfs += Printf(id, preds, pable, getId(clock).asInstanceOf[Clock])
case other =>
}
})
@@ -418,7 +418,7 @@ object Select {
* @param pable
* @param clock
*/
- case class Printf(preds: Seq[Predicate], pable: Printable, clock: Clock) extends Serializeable {
+ case class Printf(id: printf.Printf, preds: Seq[Predicate], pable: Printable, clock: Clock) extends Serializeable {
def serialize: String = {
s"printf when(${preds.map(_.serialize).mkString(" & ")}) on ${getName(clock)}: $pable"
}
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index 53d5c6ce..47849d91 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -75,11 +75,11 @@ private class Emitter(circuit: Circuit) {
case e: BulkConnect => s"${e.loc1.fullName(ctx)} <- ${e.loc2.fullName(ctx)}"
case e: Attach => e.locs.map(_.fullName(ctx)).mkString("attach (", ", ", ")")
case e: Stop => s"stop(${e.clock.fullName(ctx)}, UInt<1>(1), ${e.ret})"
- case e: Printf =>
+ case e: chisel3.internal.firrtl.Printf =>
val (fmt, args) = e.pable.unpack(ctx)
val printfArgs = Seq(e.clock.fullName(ctx), "UInt<1>(1)",
"\"" + printf.format(fmt) + "\"") ++ args
- printfArgs mkString ("printf(", ", ", ")")
+ (printfArgs mkString ("printf(", ", ", ")")) + s": ${e.name}"
case e: Verification[_] =>
s"""${e.op}(${e.clock.fullName(ctx)}, ${e.predicate.fullName(ctx)}, UInt<1>(1), "${printf.format(e.message)}") : ${e.name}"""
case e: DefInvalid => s"${e.arg.fullName(ctx)} is invalid"