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authorJack Koenig2018-11-21 15:34:42 -0800
committerJack Koenig2018-12-04 13:13:13 -0800
commit3db21bd8e5a32c29efa55494d180dac4d22589e5 (patch)
treec21edf9bc9c5f2f42ec5716a829145024bb82862 /src/main
parent121635ed26c8a9852c827d6c0729515337604d08 (diff)
Add asBool, deprecate toBool
Diffstat (limited to 'src/main')
-rw-r--r--src/main/scala/chisel3/compatibility.scala2
-rw-r--r--src/main/scala/chisel3/testers/BasicTester.scala2
-rw-r--r--src/main/scala/chisel3/util/Bitwise.scala2
-rw-r--r--src/main/scala/chisel3/util/ImplicitConversions.scala2
4 files changed, 4 insertions, 4 deletions
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 1d0c0ff7..969a31eb 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -250,7 +250,7 @@ package object Chisel { // scalastyle:ignore package.object.name
val Mux = chisel3.core.Mux
type Reset = chisel3.core.Reset
- implicit def resetToBool(reset: Reset): Bool = reset.toBool
+ implicit def resetToBool(reset: Reset): Bool = reset.asBool
import chisel3.core.Param
abstract class BlackBox(params: Map[String, Param] = Map.empty[String, Param]) extends chisel3.core.BlackBox(params) {
diff --git a/src/main/scala/chisel3/testers/BasicTester.scala b/src/main/scala/chisel3/testers/BasicTester.scala
index 1f988a3b..c21a2cdd 100644
--- a/src/main/scala/chisel3/testers/BasicTester.scala
+++ b/src/main/scala/chisel3/testers/BasicTester.scala
@@ -25,7 +25,7 @@ class BasicTester extends Module() {
*/
def stop()(implicit sourceInfo: SourceInfo) {
// TODO: rewrite this using library-style SourceInfo passing.
- when (!reset.toBool) {
+ when (!reset.asBool) {
pushCommand(Stop(sourceInfo, clock.ref, 0))
}
}
diff --git a/src/main/scala/chisel3/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala
index dc10d36d..956b8262 100644
--- a/src/main/scala/chisel3/util/Bitwise.scala
+++ b/src/main/scala/chisel3/util/Bitwise.scala
@@ -69,7 +69,7 @@ object Fill {
case 0 => UInt(0.W)
case 1 => x
case _ if x.isWidthKnown && x.getWidth == 1 =>
- Mux(x.toBool, ((BigInt(1) << n) - 1).asUInt(n.W), 0.U(n.W))
+ Mux(x.asBool, ((BigInt(1) << n) - 1).asUInt(n.W), 0.U(n.W))
case _ =>
val nBits = log2Ceil(n + 1)
val p2 = Array.ofDim[UInt](nBits)
diff --git a/src/main/scala/chisel3/util/ImplicitConversions.scala b/src/main/scala/chisel3/util/ImplicitConversions.scala
index 994ac735..24ea0470 100644
--- a/src/main/scala/chisel3/util/ImplicitConversions.scala
+++ b/src/main/scala/chisel3/util/ImplicitConversions.scala
@@ -13,5 +13,5 @@ object ImplicitConversions {
// The explicit fromIntToLiteral resolves an ambiguous conversion between fromIntToLiteral and
// UInt.asUInt.
implicit def intToUInt(x: Int): UInt = chisel3.core.fromIntToLiteral(x).asUInt
- implicit def booleanToBool(x: Boolean): Bool = x.asBool
+ implicit def booleanToBool(x: Boolean): Bool = x.B
}