clean up Id and Builder.globalRefMap

4 files changed, 58 insertions, 56 deletions

diff --git a/src/main/scala/Chisel/Builder.scala b/src/main/scala/Chisel/Builder.scala
index 723470d0..cbc94e93 100644
--- a/src/main/scala/Chisel/Builder.scala
+++ b/src/main/scala/Chisel/Builder.scala
@@ -2,6 +2,30 @@ package Chisel
 import scala.util.DynamicVariable
 import scala.collection.mutable.{ArrayBuffer, HashMap}
 
+private class Namespace(parent: Option[Namespace], keywords: Option[Set[String]]) {
+  private var i = 0L
+  private val names = collection.mutable.HashSet[String]()
+  def forbidden =  keywords.getOrElse(Set()) ++ names
+
+  private def rename(n: String) = { i += 1; s"${n}_${i}" }
+
+  def contains(elem: String): Boolean = {
+    forbidden.contains(elem) ||
+      parent.map(_ contains elem).getOrElse(false)
+  }
+
+  def name(elem: String): String = {
+    val res = if(forbidden contains elem) rename(elem) else elem
+    names += res
+    res
+  }
+
+  def child(ks: Option[Set[String]]): Namespace = new Namespace(Some(this), ks)
+  def child: Namespace = new Namespace(Some(this), None)
+}
+
+private class FIRRTLNamespace extends Namespace(None, Some(Set("mem", "node", "wire", "reg", "inst")))
+
 private class IdGen {
   private var counter = -1L
   def next: Long = {
@@ -10,24 +34,33 @@ private class IdGen {
   }
 }
 
+trait HasId {
+  private[Chisel] val _id = Builder.idGen.next
+  def setRef() =  Builder.globalRefMap.setRef(this, s"T_${_id}")
+  def setRef(imm: Immediate) = Builder.globalRefMap.setRef(this, imm)
+  def setRef(name: String) = Builder.globalRefMap.setRef(this, name)
+  def setRef(parent: HasId, name: String) = Builder.globalRefMap.setField(parent, this, name)
+  def setRef(parent: HasId, index: Int) = Builder.globalRefMap.setIndex(parent, this, index)
+}
+
 class RefMap {
   private val _refmap = new HashMap[Long,Immediate]()
 
-  def setRef(id: Id, ref: Immediate): Unit =
+  def setRef(id: HasId, ref: Immediate): Unit =
     _refmap(id._id) = ref
 
-  def setRefForId(id: Id, name: String): Unit =
+  def setRef(id: HasId, name: String): Unit =
     if (!_refmap.contains(id._id))
       setRef(id, Ref(Builder.globalNamespace.name(name)))
 
-  def setFieldForId(parentid: Id, id: Id, name: String): Unit = {
+  def setField(parentid: HasId, id: HasId, name: String): Unit = {
     _refmap(id._id) = Slot(Alias(parentid), name)
   }
 
-  def setIndexForId(parentid: Id, id: Id, index: Int): Unit =
+  def setIndex(parentid: HasId, id: HasId, index: Int): Unit =
     _refmap(id._id) = Index(Alias(parentid), index)
 
-  def apply(id: Id): Immediate = _refmap(id._id)
+  def apply(id: HasId): Immediate = _refmap(id._id)
 }
 
 private class DynamicContext {
@@ -76,7 +109,7 @@ private object Builder {
   def build[T <: Module](f: => T): Circuit = {
     dynamicContextVar.withValue(Some(new DynamicContext)) {
       val mod = f
-      globalRefMap.setRefForId(mod, mod.name)
+      mod.setRef(mod.name)
       Circuit(components.last.name, components, globalRefMap, parameterDump)
     }
   }
diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala
index c30b2704..f1b92efa 100644
--- a/src/main/scala/Chisel/Core.scala
+++ b/src/main/scala/Chisel/Core.scala
@@ -32,16 +32,12 @@ object INPUT  extends Direction("input") { def flip = OUTPUT }
 object OUTPUT extends Direction("output") { def flip = INPUT }
 object NO_DIR extends Direction("?") { def flip = NO_DIR }
 
-trait Id {
-  private[Chisel] val _id = Builder.idGen.next
-}
-
 object debug {
   // TODO:
   def apply (arg: Data) = arg
 }
 
-abstract class Data(dirArg: Direction) extends Id {
+abstract class Data(dirArg: Direction) extends HasId {
   private[Chisel] val _mod: Module = dynamicContext.getCurrentModule.getOrElse(null)
   if (_mod ne null)
     _mod.addNode(this)
@@ -72,7 +68,7 @@ abstract class Data(dirArg: Direction) extends Id {
     pushCommand(Connect(this.lref, that.ref))
   private[Chisel] def bulkConnect(that: Data): Unit =
     pushCommand(BulkConnect(this.lref, that.lref))
-  private[Chisel] def collectElts = { }
+  private[Chisel] def collectElts: Unit = { }
   private[Chisel] def lref: Alias = Alias(this)
   private[Chisel] def ref: Arg = if (isLit) litArg.get else lref
   private[Chisel] def cloneTypeWidth(width: Width): this.type
@@ -220,8 +216,8 @@ class Vec[T <: Data](gen: => T, val length: Int)
   private val self = IndexedSeq.fill(length)(gen)
 
   override def collectElts: Unit =
-    for ((e, i) <- self zipWithIndex)
-      Builder.globalRefMap.setIndexForId(this, e, i)
+    for ((elt, i) <- self zipWithIndex)
+      elt.setRef(this, i)
 
   override def <> (that: Data): Unit = that match {
     case _: Vec[_] => this bulkConnect that
@@ -697,7 +693,7 @@ class Bundle extends Aggregate(NO_DIR) {
     namedElts += name -> elt
 
   override def collectElts =
-    namedElts.foreach {case(name, elt) => Builder.globalRefMap.setFieldForId(this, elt, name)}
+    for ((name, elt) <- namedElts) { elt.setRef(this, name) }
 
   override def cloneType : this.type = {
     try {
@@ -731,7 +727,7 @@ object Module {
   }
 }
 
-abstract class Module(_clock: Clock = null, _reset: Bool = null) extends Id {
+abstract class Module(_clock: Clock = null, _reset: Bool = null) extends HasId {
   private implicit val _namespace = Builder.globalNamespace.child
   private[Chisel] val _commands = ArrayBuffer[Command]()
   private[Chisel] val _nodes = ArrayBuffer[Data]()
@@ -781,17 +777,15 @@ abstract class Module(_clock: Clock = null, _reset: Bool = null) extends Id {
     _nodes.foreach(_.collectElts)
 
     // FIRRTL: the IO namespace is part of the module namespace
-    Builder.globalRefMap.setRef(io, ModuleIO(this))
-    for ((name, field) <- io.namedElts)
-      _namespace.name(name)
+    io.setRef(ModuleIO(this))
+    for((name, elt) <- io.namedElts) { _namespace.name(name) }
 
     val methods = getClass.getMethods.sortWith(_.getName > _.getName)
     for (m <- methods; if isPublicVal(m)) m.invoke(this) match {
-      case id: Id => Builder.globalRefMap.setRefForId(id, m.getName)
+      case id: HasId => id.setRef(m.getName)
       case _ =>
     }
-    for (id <- _nodes ++ _children)
-      Builder.globalRefMap.setRefForId(id, s"T_${id._id}")
+    (_nodes ++ _children).foreach(_.setRef)
     this
   }
 
diff --git a/src/main/scala/Chisel/IR.scala b/src/main/scala/Chisel/IR.scala
index b543606c..b541e1e2 100644
--- a/src/main/scala/Chisel/IR.scala
+++ b/src/main/scala/Chisel/IR.scala
@@ -47,7 +47,7 @@ abstract class Arg extends Immediate {
   def name: String
 }
 
-case class Alias(id: Id) extends Arg {
+case class Alias(id: HasId) extends Arg {
   private val refMap = Builder.globalRefMap
   override def fullName(ctx: Component) = refMap(id).fullName(ctx)
   def name = refMap(id).name
@@ -150,17 +150,17 @@ case class ClockType(flip: Boolean) extends Kind(flip)
 abstract class Command;
 abstract class Definition extends Command {
   private val refMap = Builder.globalRefMap
-  def id: Id
+  def id: HasId
   def name = refMap(id).name
 }
-case class DefFlo(id: Id, value: Float) extends Definition
-case class DefDbl(id: Id, value: Double) extends Definition
+case class DefFlo(id: HasId, value: Float) extends Definition
+case class DefDbl(id: HasId, value: Double) extends Definition
 case class DefPrim[T <: Data](id: T, op: PrimOp, args: Arg*) extends Definition
-case class DefWire(id: Id, kind: Kind) extends Definition
-case class DefRegister(id: Id, kind: Kind, clock: Arg, reset: Arg) extends Definition
-case class DefMemory(id: Id, kind: Kind, size: Int, clock: Arg) extends Definition
-case class DefSeqMemory(id: Id, kind: Kind, size: Int) extends Definition
-case class DefAccessor(id: Id, source: Alias, direction: Direction, index: Arg) extends Definition
+case class DefWire(id: HasId, kind: Kind) extends Definition
+case class DefRegister(id: HasId, kind: Kind, clock: Arg, reset: Arg) extends Definition
+case class DefMemory(id: HasId, kind: Kind, size: Int, clock: Arg) extends Definition
+case class DefSeqMemory(id: HasId, kind: Kind, size: Int) extends Definition
+case class DefAccessor(id: HasId, source: Alias, direction: Direction, index: Arg) extends Definition
 case class DefInstance(id: Module, ports: Seq[Port]) extends Definition
 case class WhenBegin(pred: Arg) extends Command
 case class WhenElse() extends Command
diff --git a/src/main/scala/Chisel/Namespace.scala b/src/main/scala/Chisel/Namespace.scala
deleted file mode 100644
index adcd9259..00000000
--- a/src/main/scala/Chisel/Namespace.scala
+++ /dev/null
@@ -1,25 +0,0 @@
-package Chisel
-
-private class Namespace(parent: Option[Namespace], keywords: Option[Set[String]]) {
-  private var i = 0L
-  private val names = collection.mutable.HashSet[String]()
-  def forbidden =  keywords.getOrElse(Set()) ++ names
-
-  private def rename(n: String) = { i += 1; s"${n}_${i}" }
-
-  def contains(elem: String): Boolean = {
-    forbidden.contains(elem) ||
-      parent.map(_ contains elem).getOrElse(false)
-  }
-
-  def name(elem: String): String = {
-    val res = if(forbidden contains elem) rename(elem) else elem
-    names += res
-    res
-  }
-
-  def child(ks: Option[Set[String]]): Namespace = new Namespace(Some(this), ks)
-  def child: Namespace = new Namespace(Some(this), None)
-}
-
-private class FIRRTLNamespace extends Namespace(None, Some(Set("mem", "node", "wire", "reg", "inst")))