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authorAndrew Waterman2016-01-16 18:48:23 -0800
committerAndrew Waterman2016-01-16 18:48:23 -0800
commitfc3587aa24132991a50fbba1fbe4dc769953a3db (patch)
treec839074b3c787cbdd36a80d56a608cc080a6a014 /src/main/scala
parente6a712b255d94e1b4d8b1c10db523100db25c721 (diff)
Disallow Muxing between bundles whose fields have different widths
Diffstat (limited to 'src/main/scala')
-rw-r--r--src/main/scala/Chisel/Bits.scala3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/main/scala/Chisel/Bits.scala b/src/main/scala/Chisel/Bits.scala
index 7505c102..d6bef0d0 100644
--- a/src/main/scala/Chisel/Bits.scala
+++ b/src/main/scala/Chisel/Bits.scala
@@ -538,6 +538,9 @@ object Mux {
// This returns an lvalue, which it most definitely should not
private def doWhen[T <: Data](cond: Bool, con: T, alt: T): T = {
require(con.getClass == alt.getClass, s"can't Mux between ${con.getClass} and ${alt.getClass}")
+ for ((c, a) <- con.flatten zip alt.flatten)
+ require(c.width == a.width, "can't Mux between aggregates of different width")
+
val res = Wire(t = alt.cloneTypeWidth(con.width max alt.width), init = alt)
when (cond) { res := con }
res