diff options
| author | Jim Lawson | 2017-05-11 15:07:30 -0700 |
|---|---|---|
| committer | GitHub | 2017-05-11 15:07:30 -0700 |
| commit | 8baa2ab806be1aa85a7a1da7b348726da1bd1d19 (patch) | |
| tree | 9c6251d52cb17830a9ce212c7630bf0d9fecf002 /src/main/scala | |
| parent | 45e235a5948a1cd15b8ccb5f437dc6f2ff80cb96 (diff) | |
Scope resources - move them down into chisel3 directory - fixes #549 (#610)
Diffstat (limited to 'src/main/scala')
| -rw-r--r-- | src/main/scala/chisel3/testers/TesterDriver.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/testers/TesterDriver.scala b/src/main/scala/chisel3/testers/TesterDriver.scala index fd3ad9ba..fc71f2b0 100644 --- a/src/main/scala/chisel3/testers/TesterDriver.scala +++ b/src/main/scala/chisel3/testers/TesterDriver.scala @@ -28,7 +28,7 @@ object TesterDriver extends BackendCompilationUtilities { // Copy CPP harness and other Verilog sources from resources into files val cppHarness = new File(path, "top.cpp") - copyResourceToFile("/top.cpp", cppHarness) + copyResourceToFile("/chisel3/top.cpp", cppHarness) val additionalVFiles = additionalVResources.map((name: String) => { val mangledResourceName = name.replace("/", "_") val out = new File(path, mangledResourceName) |