Get cleanup to compile

16 files changed, 5 insertions, 2030 deletions

diff --git a/src/main/scala/chisel3/aop/AspectLibrary.scala b/src/main/scala/chisel3/aop/AspectLibrary.scala
deleted file mode 100644
index 04ac2384..00000000
--- a/src/main/scala/chisel3/aop/AspectLibrary.scala
+++ /dev/null
@@ -1,53 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chisel3.aop
-
-import chisel3.RawModule
-import firrtl.options.{OptionsException, RegisteredLibrary, ShellOption}
-
-/** Enables adding aspects to a design from the commandline, e.g.
-  *  sbt> runMain chisel3.stage.ChiselMain --module <module> --with-aspect <aspect>
-  */
-final class AspectLibrary() extends RegisteredLibrary {
-  val name = "AspectLibrary"
-
-  import scala.reflect.runtime.universe._
-
-  private def apply(aspectName: String): Aspect[RawModule] = {
-    try {
-      // If a regular class, instantiate, otherwise try as a singleton object
-      try {
-        val x = Class.forName(aspectName).asInstanceOf[Class[_ <: Aspect[RawModule]]]
-        x.newInstance()
-      } catch {
-        case e: InstantiationException =>
-          val rm = runtimeMirror(getClass.getClassLoader)
-          val x = rm.staticModule(aspectName)
-          try {
-            rm.reflectModule(x).instance.asInstanceOf[Aspect[RawModule]]
-          } catch {
-            case _: Exception => throw e
-          }
-      }
-    } catch {
-      case e: ClassNotFoundException =>
-        throw new OptionsException(s"Unable to locate aspect '$aspectName'! (Did you misspell it?)", e)
-      case e: InstantiationException =>
-        throw new OptionsException(
-          s"Unable to create instance of aspect '$aspectName'! (Does this class take parameters?)",
-          e
-        )
-    }
-  }
-
-  val options = Seq(
-    new ShellOption[String](
-      longOption = "with-aspect",
-      toAnnotationSeq = {
-        case aspectName: String => Seq(apply(aspectName))
-      },
-      helpText = "The name/class of an aspect to compile with (must be a class/object without arguments!)",
-      helpValueName = Some("<package>.<aspect>")
-    )
-  )
-}
diff --git a/src/main/scala/chisel3/aop/Select.scala b/src/main/scala/chisel3/aop/Select.scala
deleted file mode 100644
index 738d6f31..00000000
--- a/src/main/scala/chisel3/aop/Select.scala
+++ /dev/null
@@ -1,614 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chisel3.aop
-
-import chisel3._
-import chisel3.internal.{HasId}
-import chisel3.experimental.BaseModule
-import chisel3.experimental.FixedPoint
-import chisel3.internal.firrtl.{Definition => DefinitionIR, _}
-import chisel3.experimental.hierarchy._
-import chisel3.internal.PseudoModule
-import chisel3.internal.BaseModule.ModuleClone
-import firrtl.annotations.ReferenceTarget
-import scala.reflect.runtime.universe.TypeTag
-
-import scala.collection.mutable
-import chisel3.internal.naming.chiselName
-
-/** Use to select Chisel components in a module, after that module has been constructed
-  * Useful for adding additional Chisel annotations or for use within an [[Aspect]]
-  */
-object Select {
-
-  /** Return just leaf components of expanded node
-    *
-    * @param d Component to find leafs if aggregate typed. Intermediate fields/indicies are not included
-    */
-  def getLeafs(d: Data): Seq[Data] = d match {
-    case r: Record => r.elementsIterator.flatMap(getLeafs).toSeq
-    case v: Vec[_] => v.getElements.flatMap(getLeafs)
-    case other => Seq(other)
-  }
-
-  /** Return all expanded components, including intermediate aggregate nodes
-    *
-    * @param d Component to find leafs if aggregate typed. Intermediate fields/indicies ARE included
-    */
-  def getIntermediateAndLeafs(d: Data): Seq[Data] = d match {
-    case r: Record => r +: r.elementsIterator.flatMap(getIntermediateAndLeafs).toSeq
-    case v: Vec[_] => v +: v.getElements.flatMap(getIntermediateAndLeafs)
-    case other => Seq(other)
-  }
-
-  /** Selects all instances/modules directly instantiated within given definition
-    *
-    * @param parent
-    */
-  def instancesIn(parent: Hierarchy[BaseModule]): Seq[Instance[BaseModule]] = {
-    check(parent)
-    implicit val mg = new chisel3.internal.MacroGenerated {}
-    parent.proto._component.get match {
-      case d: DefModule =>
-        d.commands.collect {
-          case d: DefInstance =>
-            d.id match {
-              case p: chisel3.internal.BaseModule.IsClone[_] =>
-                parent._lookup { x => new Instance(Clone(p)).asInstanceOf[Instance[BaseModule]] }
-              case other: BaseModule =>
-                parent._lookup { x => other }
-            }
-        }
-      case other => Nil
-    }
-  }
-
-  /** Selects all Instances of instances/modules directly instantiated within given module, of provided type
-    *
-    * @note IMPORTANT: this function requires summoning a TypeTag[T], which will fail if T is an inner class.
-    * @note IMPORTANT: this function ignores type parameters. E.g. instancesOf[List[Int]] would return List[String].
-    *
-    * @param parent hierarchy which instantiates the returned Definitions
-    */
-  def instancesOf[T <: BaseModule: TypeTag](parent: Hierarchy[BaseModule]): Seq[Instance[T]] = {
-    check(parent)
-    implicit val mg = new chisel3.internal.MacroGenerated {}
-    parent.proto._component.get match {
-      case d: DefModule =>
-        d.commands.flatMap {
-          case d: DefInstance =>
-            d.id match {
-              case p: chisel3.internal.BaseModule.IsClone[_] =>
-                val i = parent._lookup { x => new Instance(Clone(p)).asInstanceOf[Instance[BaseModule]] }
-                if (i.isA[T]) Some(i.asInstanceOf[Instance[T]]) else None
-              case other: BaseModule =>
-                val i = parent._lookup { x => other }
-                if (i.isA[T]) Some(i.asInstanceOf[Instance[T]]) else None
-            }
-          case other => None
-        }
-      case other => Nil
-    }
-  }
-
-  /** Selects all Instances directly and indirectly instantiated within given root hierarchy, of provided type
-    *
-    * @note IMPORTANT: this function requires summoning a TypeTag[T], which will fail if T is an inner class.
-    * @note IMPORTANT: this function ignores type parameters. E.g. allInstancesOf[List[Int]] would return List[String].
-    *
-    * @param root top of the hierarchy to search for instances/modules of given type
-    */
-  def allInstancesOf[T <: BaseModule: TypeTag](root: Hierarchy[BaseModule]): Seq[Instance[T]] = {
-    val soFar = if (root.isA[T]) Seq(root.toInstance.asInstanceOf[Instance[T]]) else Nil
-    val allLocalInstances = instancesIn(root)
-    soFar ++ (allLocalInstances.flatMap(allInstancesOf[T]))
-  }
-
-  /** Selects the Definitions of all instances/modules directly instantiated within given module
-    *
-    * @param parent
-    */
-  def definitionsIn(parent: Hierarchy[BaseModule]): Seq[Definition[BaseModule]] = {
-    type DefType = Definition[BaseModule]
-    implicit val mg = new chisel3.internal.MacroGenerated {}
-    check(parent)
-    val defs = parent.proto._component.get match {
-      case d: DefModule =>
-        d.commands.collect {
-          case i: DefInstance =>
-            i.id match {
-              case p: chisel3.internal.BaseModule.IsClone[_] =>
-                parent._lookup { x => new Definition(Proto(p.getProto)).asInstanceOf[Definition[BaseModule]] }
-              case other: BaseModule =>
-                parent._lookup { x => other.toDefinition }
-            }
-        }
-      case other => Nil
-    }
-    val (_, defList) = defs.foldLeft((Set.empty[DefType], List.empty[DefType])) {
-      case ((set, list), definition: Definition[BaseModule]) =>
-        if (set.contains(definition)) (set, list) else (set + definition, definition +: list)
-    }
-    defList.reverse
-  }
-
-  /** Selects all Definitions of instances/modules directly instantiated within given module, of provided type
-    *
-    * @note IMPORTANT: this function requires summoning a TypeTag[T], which will fail if T is an inner class.
-    * @note IMPORTANT: this function ignores type parameters. E.g. definitionsOf[List[Int]] would return List[String].
-    *
-    * @param parent hierarchy which instantiates the returned Definitions
-    */
-  def definitionsOf[T <: BaseModule: TypeTag](parent: Hierarchy[BaseModule]): Seq[Definition[T]] = {
-    check(parent)
-    implicit val mg = new chisel3.internal.MacroGenerated {}
-    type DefType = Definition[T]
-    val defs = parent.proto._component.get match {
-      case d: DefModule =>
-        d.commands.flatMap {
-          case d: DefInstance =>
-            d.id match {
-              case p: chisel3.internal.BaseModule.IsClone[_] =>
-                val d = parent._lookup { x => new Definition(Clone(p)).asInstanceOf[Definition[BaseModule]] }
-                if (d.isA[T]) Some(d.asInstanceOf[Definition[T]]) else None
-              case other: BaseModule =>
-                val d = parent._lookup { x => other.toDefinition }
-                if (d.isA[T]) Some(d.asInstanceOf[Definition[T]]) else None
-            }
-          case other => None
-        }
-    }
-    val (_, defList) = defs.foldLeft((Set.empty[DefType], List.empty[DefType])) {
-      case ((set, list), definition: Definition[T]) =>
-        if (set.contains(definition)) (set, list) else (set + definition, definition +: list)
-    }
-    defList.reverse
-  }
-
-  /** Selects all Definition's directly and indirectly instantiated within given root hierarchy, of provided type
-    *
-    * @note IMPORTANT: this function requires summoning a TypeTag[T], which will fail if T is an inner class, i.e.
-    *   a class defined within another class.
-    * @note IMPORTANT: this function ignores type parameters. E.g. allDefinitionsOf[List[Int]] would return List[String].
-    *
-    * @param root top of the hierarchy to search for definitions of given type
-    */
-  def allDefinitionsOf[T <: BaseModule: TypeTag](root: Hierarchy[BaseModule]): Seq[Definition[T]] = {
-    type DefType = Definition[T]
-    val allDefSet = mutable.HashSet[Definition[BaseModule]]()
-    val defSet = mutable.HashSet[DefType]()
-    val defList = mutable.ArrayBuffer[DefType]()
-    def rec(hier: Definition[BaseModule]): Unit = {
-      if (hier.isA[T] && !defSet.contains(hier.asInstanceOf[DefType])) {
-        defSet += hier.asInstanceOf[DefType]
-        defList += hier.asInstanceOf[DefType]
-      }
-      allDefSet += hier
-      val allDefs = definitionsIn(hier)
-      allDefs.collect {
-        case d if !allDefSet.contains(d) => rec(d)
-      }
-    }
-    rec(root.toDefinition)
-    defList.toList
-  }
-
-  /** Collects all components selected by collector within module and all children modules it instantiates
-    *   directly or indirectly
-    * Accepts a collector function, rather than a collector partial function (see [[collectDeep]])
-    *
-    * @note This API will not work with the new experimental hierarchy package. Instead, use allInstancesOf or allDefinitionsOf.
-    *
-    * @param module Module to collect components, as well as all children module it directly and indirectly instantiates
-    * @param collector Collector function to pick, given a module, which components to collect
-    * @param tag Required for generics to work, should ignore this
-    * @tparam T Type of the component that will be collected
-    */
-  def getDeep[T](module: BaseModule)(collector: BaseModule => Seq[T]): Seq[T] = {
-    check(module)
-    val myItems = collector(module)
-    val deepChildrenItems = instances(module).flatMap { i =>
-      getDeep(i)(collector)
-    }
-    myItems ++ deepChildrenItems
-  }
-
-  /** Collects all components selected by collector within module and all children modules it instantiates
-    *   directly or indirectly
-    * Accepts a collector partial function, rather than a collector function (see [[getDeep]])
-    *
-    * @note This API will not work with the new experimental hierarchy package. Instead, use allInstancesOf or allDefinitionsOf.
-    *
-    * @param module Module to collect components, as well as all children module it directly and indirectly instantiates
-    * @param collector Collector partial function to pick, given a module, which components to collect
-    * @param tag Required for generics to work, should ignore this
-    * @tparam T Type of the component that will be collected
-    */
-  def collectDeep[T](module: BaseModule)(collector: PartialFunction[BaseModule, T]): Iterable[T] = {
-    check(module)
-    val myItems = collector.lift(module)
-    val deepChildrenItems = instances(module).flatMap { i =>
-      collectDeep(i)(collector)
-    }
-    myItems ++ deepChildrenItems
-  }
-
-  /** Selects all modules directly instantiated within given module
-    *
-    * @note This API will not work with the new experimental hierarchy package. Instead, use instancesIn or definitionsIn.
-    *
-    * @param module
-    */
-  def instances(module: BaseModule): Seq[BaseModule] = {
-    check(module)
-    module._component.get match {
-      case d: DefModule =>
-        d.commands.flatMap {
-          case i: DefInstance =>
-            i.id match {
-              case m: ModuleClone[_] if !m._madeFromDefinition => None
-              case _: PseudoModule =>
-                throw new Exception(
-                  "instances, collectDeep, and getDeep are currently incompatible with Definition/Instance!"
-                )
-              case other => Some(other)
-            }
-          case _ => None
-        }
-      case other => Nil
-    }
-  }
-
-  /** Selects all registers directly instantiated within given module
-    * @param module
-    */
-  def registers(module: BaseModule): Seq[Data] = {
-    check(module)
-    module._component.get.asInstanceOf[DefModule].commands.collect {
-      case r: DefReg     => r.id
-      case r: DefRegInit => r.id
-    }
-  }
-
-  /** Selects all ios on a given module
-    * @param module
-    */
-  def ios(module: BaseModule): Seq[Data] = {
-    check(module)
-    module._component.get.asInstanceOf[DefModule].ports.map(_.id)
-  }
-
-  /** Selects all ios directly on a given Instance or Definition of a module
-    * @param parent the Definition or Instance to get the IOs of
-    */
-  def ios[T <: BaseModule](parent: Hierarchy[T]): Seq[Data] = {
-    check(parent)
-    implicit val mg = new chisel3.internal.MacroGenerated {}
-    parent._lookup { x => ios(parent.proto) }
-  }
-
-  /** Selects all SyncReadMems directly contained within given module
-    * @param module
-    */
-  def syncReadMems(module: BaseModule): Seq[SyncReadMem[_]] = {
-    check(module)
-    module._component.get.asInstanceOf[DefModule].commands.collect {
-      case r: DefSeqMemory => r.id.asInstanceOf[SyncReadMem[_]]
-    }
-  }
-
-  /** Selects all Mems directly contained within given module
-    * @param module
-    */
-  def mems(module: BaseModule): Seq[Mem[_]] = {
-    check(module)
-    module._component.get.asInstanceOf[DefModule].commands.collect {
-      case r: DefMemory => r.id.asInstanceOf[Mem[_]]
-    }
-  }
-
-  /** Selects all arithmetic or logical operators directly instantiated within given module
-    * @param module
-    */
-  def ops(module: BaseModule): Seq[(String, Data)] = {
-    check(module)
-    module._component.get.asInstanceOf[DefModule].commands.collect {
-      case d: DefPrim[_] => (d.op.name, d.id)
-    }
-  }
-
-  /** Selects a kind of arithmetic or logical operator directly instantiated within given module
-    * The kind of operators are contained in [[chisel3.internal.firrtl.PrimOp]]
-    * @param opKind the kind of operator, e.g. "mux", "add", or "bits"
-    * @param module
-    */
-  def ops(opKind: String)(module: BaseModule): Seq[Data] = {
-    check(module)
-    module._component.get.asInstanceOf[DefModule].commands.collect {
-      case d: DefPrim[_] if d.op.name == opKind => d.id
-    }
-  }
-
-  /** Selects all wires in a module
-    * @param module
-    */
-  def wires(module: BaseModule): Seq[Data] = {
-    check(module)
-    module._component.get.asInstanceOf[DefModule].commands.collect {
-      case r: DefWire => r.id
-    }
-  }
-
-  /** Selects all memory ports, including their direction and memory
-    * @param module
-    */
-  def memPorts(module: BaseModule): Seq[(Data, MemPortDirection, MemBase[_])] = {
-    check(module)
-    module._component.get.asInstanceOf[DefModule].commands.collect {
-      case r: DefMemPort[_] => (r.id, r.dir, r.source.id.asInstanceOf[MemBase[_ <: Data]])
-    }
-  }
-
-  /** Selects all memory ports of a given direction, including their memory
-    * @param dir The direction of memory ports to select
-    * @param module
-    */
-  def memPorts(dir: MemPortDirection)(module: BaseModule): Seq[(Data, MemBase[_])] = {
-    check(module)
-    module._component.get.asInstanceOf[DefModule].commands.collect {
-      case r: DefMemPort[_] if r.dir == dir => (r.id, r.source.id.asInstanceOf[MemBase[_ <: Data]])
-    }
-  }
-
-  /** Selects all components who have been set to be invalid, even if they are later connected to
-    * @param module
-    */
-  def invalids(module: BaseModule): Seq[Data] = {
-    check(module)
-    module._component.get.asInstanceOf[DefModule].commands.collect {
-      case DefInvalid(_, arg) => getData(arg)
-    }
-  }
-
-  /** Selects all components who are attached to a given signal, within a module
-    * @param module
-    */
-  def attachedTo(module: BaseModule)(signal: Data): Set[Data] = {
-    check(module)
-    module._component.get
-      .asInstanceOf[DefModule]
-      .commands
-      .collect {
-        case Attach(_, seq) if seq.contains(signal) => seq
-      }
-      .flatMap { seq => seq.map(_.id.asInstanceOf[Data]) }
-      .toSet
-  }
-
-  /** Selects all connections to a signal or its parent signal(s) (if the signal is an element of an aggregate signal)
-    * The when predicates surrounding each connection are included in the returned values
-    *
-    * E.g. if signal = io.foo.bar, connectionsTo will return all connections to io, io.foo, and io.bar
-    * @param module
-    * @param signal
-    */
-  def connectionsTo(module: BaseModule)(signal: Data): Seq[PredicatedConnect] = {
-    check(module)
-    val sensitivitySignals = getIntermediateAndLeafs(signal).toSet
-    val predicatedConnects = mutable.ArrayBuffer[PredicatedConnect]()
-    val isPort = module._component.get
-      .asInstanceOf[DefModule]
-      .ports
-      .flatMap { p => getIntermediateAndLeafs(p.id) }
-      .contains(signal)
-    var prePredicates: Seq[Predicate] = Nil
-    var seenDef = isPort
-    searchWhens(
-      module,
-      (cmd: Command, preds) => {
-        cmd match {
-          case cmd: DefinitionIR if cmd.id.isInstanceOf[Data] =>
-            val x = getIntermediateAndLeafs(cmd.id.asInstanceOf[Data])
-            if (x.contains(signal)) prePredicates = preds
-          case Connect(_, loc @ Node(d: Data), exp) =>
-            val effected = getEffected(loc).toSet
-            if (sensitivitySignals.intersect(effected).nonEmpty) {
-              val expData = getData(exp)
-              prePredicates.reverse
-                .zip(preds.reverse)
-                .foreach(x => assert(x._1 == x._2, s"Prepredicates $x must match for signal $signal"))
-              predicatedConnects += PredicatedConnect(preds.dropRight(prePredicates.size), d, expData, isBulk = false)
-            }
-          case BulkConnect(_, loc @ Node(d: Data), exp) =>
-            val effected = getEffected(loc).toSet
-            if (sensitivitySignals.intersect(effected).nonEmpty) {
-              val expData = getData(exp)
-              prePredicates.reverse
-                .zip(preds.reverse)
-                .foreach(x => assert(x._1 == x._2, s"Prepredicates $x must match for signal $signal"))
-              predicatedConnects += PredicatedConnect(preds.dropRight(prePredicates.size), d, expData, isBulk = true)
-            }
-          case other =>
-        }
-      }
-    )
-    predicatedConnects.toSeq
-  }
-
-  /** Selects all stop statements, and includes the predicates surrounding the stop statement
-    *
-    * @param module
-    */
-  def stops(module: BaseModule): Seq[Stop] = {
-    val stops = mutable.ArrayBuffer[Stop]()
-    searchWhens(
-      module,
-      (cmd: Command, preds: Seq[Predicate]) => {
-        cmd match {
-          case chisel3.internal.firrtl.Stop(_, _, clock, ret) =>
-            stops += Stop(preds, ret, getId(clock).asInstanceOf[Clock])
-          case other =>
-        }
-      }
-    )
-    stops.toSeq
-  }
-
-  /** Selects all printf statements, and includes the predicates surrounding the printf statement
-    *
-    * @param module
-    */
-  def printfs(module: BaseModule): Seq[Printf] = {
-    val printfs = mutable.ArrayBuffer[Printf]()
-    searchWhens(
-      module,
-      (cmd: Command, preds: Seq[Predicate]) => {
-        cmd match {
-          case chisel3.internal.firrtl.Printf(id, _, clock, pable) =>
-            printfs += Printf(id, preds, pable, getId(clock).asInstanceOf[Clock])
-          case other =>
-        }
-      }
-    )
-    printfs.toSeq
-  }
-
-  // Checks that a module has finished its construction
-  private def check(module: BaseModule): Unit = {
-    require(module.isClosed, "Can't use Selector on modules that have not finished construction!")
-    require(module._component.isDefined, "Can't use Selector on modules that don't have components!")
-  }
-  private def check(hierarchy: Hierarchy[BaseModule]): Unit = check(hierarchy.proto)
-
-  // Given a loc, return all subcomponents of id that could be assigned to in connect
-  private def getEffected(a: Arg): Seq[Data] = a match {
-    case Node(id: Data) => getIntermediateAndLeafs(id)
-    case Slot(imm, name)   => Seq(imm.id.asInstanceOf[Record].elements(name))
-    case Index(imm, value) => getEffected(imm)
-  }
-
-  // Given an arg, return the corresponding id. Don't use on a loc of a connect.
-  private def getId(a: Arg): HasId = a match {
-    case Node(id) => id
-    case l: ULit  => l.num.U(l.w)
-    case l: SLit  => l.num.S(l.w)
-    case l: FPLit => FixedPoint(l.num, l.w, l.binaryPoint)
-    case other =>
-      sys.error(s"Something went horribly wrong! I was expecting ${other} to be a lit or a node!")
-  }
-
-  private def getData(a: Arg): Data = a match {
-    case Node(data: Data) => data
-    case other =>
-      sys.error(s"Something went horribly wrong! I was expecting ${other} to be Data!")
-  }
-
-  // Given an id, either get its name or its value, if its a lit
-  private def getName(i: HasId): String = try {
-    i.toTarget match {
-      case r: ReferenceTarget =>
-        val str = r.serialize
-        str.splitAt(str.indexOf('>'))._2.drop(1)
-    }
-  } catch {
-    case e: ChiselException =>
-      i.getOptionRef.get match {
-        case l: LitArg => l.num.intValue.toString
-      }
-  }
-
-  // Collects when predicates as it searches through a module, then applying processCommand to non-when related commands
-  private def searchWhens(module: BaseModule, processCommand: (Command, Seq[Predicate]) => Unit) = {
-    check(module)
-    module._component.get.asInstanceOf[DefModule].commands.foldLeft((Seq.empty[Predicate], Option.empty[Predicate])) {
-      (blah, cmd) =>
-        (blah, cmd) match {
-          case ((preds, o), cmd) =>
-            cmd match {
-              case WhenBegin(_, Node(pred: Bool)) => (When(pred) +: preds, None)
-              case WhenBegin(_, l: LitArg) if l.num == BigInt(1) => (When(true.B) +: preds, None)
-              case WhenBegin(_, l: LitArg) if l.num == BigInt(0) => (When(false.B) +: preds, None)
-              case other: WhenBegin =>
-                sys.error(s"Something went horribly wrong! I was expecting ${other.pred} to be a lit or a bool!")
-              case _: WhenEnd => (preds.tail, Some(preds.head))
-              case AltBegin(_) if o.isDefined => (o.get.not +: preds, o)
-              case _: AltBegin =>
-                sys.error(s"Something went horribly wrong! I was expecting ${o} to be nonEmpty!")
-              case OtherwiseEnd(_, _) => (preds.tail, None)
-              case other =>
-                processCommand(cmd, preds)
-                (preds, o)
-            }
-        }
-    }
-  }
-
-  trait Serializeable {
-    def serialize: String
-  }
-
-  /** Used to indicates a when's predicate (or its otherwise predicate)
-    */
-  trait Predicate extends Serializeable {
-    val bool: Bool
-    def not: Predicate
-  }
-
-  /** Used to represent [[chisel3.when]] predicate
-    *
-    * @param bool the when predicate
-    */
-  case class When(bool: Bool) extends Predicate {
-    def not:       WhenNot = WhenNot(bool)
-    def serialize: String = s"${getName(bool)}"
-  }
-
-  /** Used to represent the `otherwise` predicate of a [[chisel3.when]]
-    *
-    * @param bool the when predicate corresponding to this otherwise predicate
-    */
-  case class WhenNot(bool: Bool) extends Predicate {
-    def not:       When = When(bool)
-    def serialize: String = s"!${getName(bool)}"
-  }
-
-  /** Used to represent a connection or bulk connection
-    *
-    * Additionally contains the sequence of when predicates seen when the connection is declared
-    *
-    * @param preds
-    * @param loc
-    * @param exp
-    * @param isBulk
-    */
-  case class PredicatedConnect(preds: Seq[Predicate], loc: Data, exp: Data, isBulk: Boolean) extends Serializeable {
-    def serialize: String = {
-      val moduleTarget = loc.toTarget.moduleTarget.serialize
-      s"$moduleTarget: when(${preds.map(_.serialize).mkString(" & ")}): ${getName(loc)} ${if (isBulk) "<>" else ":="} ${getName(exp)}"
-    }
-  }
-
-  /** Used to represent a [[chisel3.stop]]
-    *
-    * @param preds
-    * @param ret
-    * @param clock
-    */
-  case class Stop(preds: Seq[Predicate], ret: Int, clock: Clock) extends Serializeable {
-    def serialize: String = {
-      s"stop when(${preds.map(_.serialize).mkString(" & ")}) on ${getName(clock)}: $ret"
-    }
-  }
-
-  /** Used to represent a [[chisel3.printf]]
-    *
-    * @param preds
-    * @param pable
-    * @param clock
-    */
-  case class Printf(id: printf.Printf, preds: Seq[Predicate], pable: Printable, clock: Clock) extends Serializeable {
-    def serialize: String = {
-      s"printf when(${preds.map(_.serialize).mkString(" & ")}) on ${getName(clock)}: $pable"
-    }
-  }
-}
diff --git a/src/main/scala/chisel3/aop/injecting/InjectStatement.scala b/src/main/scala/chisel3/aop/injecting/InjectStatement.scala
deleted file mode 100644
index dbe1fd7b..00000000
--- a/src/main/scala/chisel3/aop/injecting/InjectStatement.scala
+++ /dev/null
@@ -1,26 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chisel3.aop.injecting
-
-import chisel3.stage.phases.AspectPhase
-import firrtl.annotations.{Annotation, ModuleTarget, NoTargetAnnotation, SingleTargetAnnotation}
-
-/** Contains all information needed to inject statements into a module
-  *
-  * Generated when a [[InjectingAspect]] is consumed by a [[AspectPhase]]
-  * Consumed by [[InjectingTransform]]
-  *
-  * @param module Module to inject code into at the end of the module
-  * @param s Statements to inject
-  * @param modules Additional modules that may be instantiated by s
-  * @param annotations Additional annotations that should be passed down compiler
-  */
-case class InjectStatement(
-  module:      ModuleTarget,
-  s:           firrtl.ir.Statement,
-  modules:     Seq[firrtl.ir.DefModule],
-  annotations: Seq[Annotation])
-    extends SingleTargetAnnotation[ModuleTarget] {
-  val target: ModuleTarget = module
-  override def duplicate(n: ModuleTarget): Annotation = this.copy(module = n)
-}
diff --git a/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala b/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala
deleted file mode 100644
index ecce19e1..00000000
--- a/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala
+++ /dev/null
@@ -1,108 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chisel3.aop.injecting
-
-import chisel3.{withClockAndReset, Module, ModuleAspect, RawModule}
-import chisel3.aop._
-import chisel3.internal.{Builder, DynamicContext}
-import chisel3.internal.firrtl.DefModule
-import chisel3.stage.{ChiselOptions, DesignAnnotation}
-import firrtl.annotations.ModuleTarget
-import firrtl.stage.RunFirrtlTransformAnnotation
-import firrtl.options.Viewer.view
-import firrtl.{ir, _}
-
-import scala.collection.mutable
-
-/** Aspect to inject Chisel code into a module of type M
-  *
-  * @param selectRoots Given top-level module, pick the instances of a module to apply the aspect (root module)
-  * @param injection Function to generate Chisel hardware that will be injected to the end of module m
-  *                  Signals in m can be referenced and assigned to as if inside m (yes, it is a bit magical)
-  * @tparam T Type of top-level module
-  * @tparam M Type of root module (join point)
-  */
-case class InjectingAspect[T <: RawModule, M <: RawModule](
-  selectRoots: T => Iterable[M],
-  injection:   M => Unit)
-    extends InjectorAspect[T, M](
-      selectRoots,
-      injection
-    )
-
-/** Extend to inject Chisel code into a module of type M
-  *
-  * @param selectRoots Given top-level module, pick the instances of a module to apply the aspect (root module)
-  * @param injection Function to generate Chisel hardware that will be injected to the end of module m
-  *                  Signals in m can be referenced and assigned to as if inside m (yes, it is a bit magical)
-  * @tparam T Type of top-level module
-  * @tparam M Type of root module (join point)
-  */
-abstract class InjectorAspect[T <: RawModule, M <: RawModule](
-  selectRoots: T => Iterable[M],
-  injection:   M => Unit)
-    extends Aspect[T] {
-  final def toAnnotation(top: T): AnnotationSeq = {
-    val moduleNames =
-      Select.allDefinitionsOf[chisel3.experimental.BaseModule](top.toDefinition).map { i => i.toTarget.module }.toSeq
-    toAnnotation(selectRoots(top), top.name, moduleNames)
-  }
-
-  /** Returns annotations which contain all injection logic
-    *
-    * @param modules The modules to inject into
-    * @param circuit Top level circuit
-    * @param moduleNames The names of all existing modules in the original circuit, to avoid name collisions
-    * @return
-    */
-  final def toAnnotation(modules: Iterable[M], circuit: String, moduleNames: Seq[String]): AnnotationSeq = {
-    RunFirrtlTransformAnnotation(new InjectingTransform) +: modules.map { module =>
-      val chiselOptions = view[ChiselOptions](annotationsInAspect)
-      val dynamicContext =
-        new DynamicContext(
-          annotationsInAspect,
-          chiselOptions.throwOnFirstError,
-          chiselOptions.warnReflectiveNaming,
-          chiselOptions.warningsAsErrors
-        )
-      // Add existing module names into the namespace. If injection logic instantiates new modules
-      //  which would share the same name, they will get uniquified accordingly
-      moduleNames.foreach { n =>
-        dynamicContext.globalNamespace.name(n)
-      }
-
-      val (chiselIR, _) = Builder.build(
-        Module(new ModuleAspect(module) {
-          module match {
-            case x: Module    => withClockAndReset(x.clock, x.reset) { injection(module) }
-            case x: RawModule => injection(module)
-          }
-        }),
-        dynamicContext
-      )
-
-      val comps = chiselIR.components.map {
-        case x: DefModule if x.name == module.name => x.copy(id = module)
-        case other => other
-      }
-
-      val annotations = chiselIR.annotations.map(_.toFirrtl).filterNot { a => a.isInstanceOf[DesignAnnotation[_]] }
-
-      /** Statements to be injected via aspect. */
-      val stmts = mutable.ArrayBuffer[ir.Statement]()
-
-      /** Modules to be injected via aspect. */
-      val modules = Aspect.getFirrtl(chiselIR.copy(components = comps)).modules.flatMap {
-        // for "container" modules, inject their statements
-        case m: firrtl.ir.Module if m.name == module.name =>
-          stmts += m.body
-          Nil
-        // for modules to be injected
-        case other: firrtl.ir.DefModule =>
-          Seq(other)
-      }
-
-      InjectStatement(ModuleTarget(circuit, module.name), ir.Block(stmts.toSeq), modules, annotations)
-    }.toSeq
-  }
-}
diff --git a/src/main/scala/chisel3/aop/injecting/InjectingTransform.scala b/src/main/scala/chisel3/aop/injecting/InjectingTransform.scala
deleted file mode 100644
index 8a0b6ecb..00000000
--- a/src/main/scala/chisel3/aop/injecting/InjectingTransform.scala
+++ /dev/null
@@ -1,46 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chisel3.aop.injecting
-
-import firrtl.{ir, ChirrtlForm, CircuitForm, CircuitState, Transform}
-
-import scala.collection.mutable
-
-/** Appends statements contained in [[InjectStatement]] annotations to the end of their corresponding modules
-  *
-  * Implemented with Chisel Aspects and the [[chisel3.aop.injecting]] library
-  */
-class InjectingTransform extends Transform {
-  override def inputForm:  CircuitForm = ChirrtlForm
-  override def outputForm: CircuitForm = ChirrtlForm
-
-  override def execute(state: CircuitState): CircuitState = {
-
-    val addStmtMap = mutable.HashMap[String, Seq[ir.Statement]]()
-    val addModules = mutable.ArrayBuffer[ir.DefModule]()
-
-    // Populate addStmtMap and addModules, return annotations in InjectStatements, and omit InjectStatement annotation
-    val newAnnotations = state.annotations.flatMap {
-      case InjectStatement(mt, s, addedModules, annotations) =>
-        addModules ++= addedModules
-        addStmtMap(mt.module) = s +: addStmtMap.getOrElse(mt.module, Nil)
-        annotations
-      case other => Seq(other)
-    }
-
-    // Append all statements to end of corresponding modules
-    val newModules = state.circuit.modules.map { m: ir.DefModule =>
-      m match {
-        case m: ir.Module if addStmtMap.contains(m.name) =>
-          m.copy(body = ir.Block(m.body +: addStmtMap(m.name)))
-        case m: _root_.firrtl.ir.ExtModule if addStmtMap.contains(m.name) =>
-          ir.Module(m.info, m.name, m.ports, ir.Block(addStmtMap(m.name)))
-        case other: ir.DefModule => other
-      }
-    }
-
-    // Return updated circuit and annotations
-    val newCircuit = state.circuit.copy(modules = newModules ++ addModules)
-    state.copy(annotations = newAnnotations, circuit = newCircuit)
-  }
-}
diff --git a/src/main/scala/chisel3/aop/inspecting/InspectingAspect.scala b/src/main/scala/chisel3/aop/inspecting/InspectingAspect.scala
deleted file mode 100644
index 1340f253..00000000
--- a/src/main/scala/chisel3/aop/inspecting/InspectingAspect.scala
+++ /dev/null
@@ -1,26 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chisel3.aop.inspecting
-
-import chisel3.RawModule
-import chisel3.aop.Aspect
-import firrtl.AnnotationSeq
-
-/** Use for inspecting an elaborated design and printing out results
-  *
-  * @param inspect Given top-level design, print things and return nothing
-  * @tparam T Type of top-level module
-  */
-case class InspectingAspect[T <: RawModule](inspect: T => Unit) extends InspectorAspect[T](inspect)
-
-/** Extend to make custom inspections of an elaborated design and printing out results
-  *
-  * @param inspect Given top-level design, print things and return nothing
-  * @tparam T Type of top-level module
-  */
-abstract class InspectorAspect[T <: RawModule](inspect: T => Unit) extends Aspect[T] {
-  override def toAnnotation(top: T): AnnotationSeq = {
-    inspect(top)
-    Nil
-  }
-}
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
deleted file mode 100644
index d140725f..00000000
--- a/src/main/scala/chisel3/compatibility.scala
+++ /dev/null
@@ -1,693 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-/** The Chisel compatibility package allows legacy users to continue using the `Chisel` (capital C) package name
-  *  while moving to the more standard package naming convention `chisel3` (lowercase c).
-  */
-import chisel3._ // required for implicit conversions.
-import chisel3.util.random.FibonacciLFSR
-import chisel3.stage.{phases, ChiselCircuitAnnotation, ChiselOutputFileAnnotation, ChiselStage}
-
-package object Chisel {
-  import chisel3.internal.firrtl.Width
-
-  import scala.language.experimental.macros
-  import scala.annotation.StaticAnnotation
-  import scala.annotation.compileTimeOnly
-  import scala.language.implicitConversions
-
-  implicit val defaultCompileOptions = chisel3.ExplicitCompileOptions.NotStrict
-
-  abstract class Direction
-  case object INPUT extends Direction
-  case object OUTPUT extends Direction
-  case object NODIR extends Direction
-
-  val Input = chisel3.Input
-  val Output = chisel3.Output
-
-  object Flipped {
-    def apply[T <: Data](target: T): T = chisel3.Flipped[T](target)
-  }
-
-  implicit class AddDirectionToData[T <: Data](target: T) {
-    def asInput:  T = Input(target)
-    def asOutput: T = Output(target)
-    def flip:     T = Flipped(target)
-
-    @deprecated(
-      "Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead",
-      "Chisel 3.5"
-    )
-    def flip(dummy: Int*): T = flip
-  }
-
-  implicit class AddDirMethodToData[T <: Data](target: T) {
-    import chisel3.ActualDirection
-    import chisel3.experimental.DataMirror
-    import chisel3.internal.requireIsHardware
-
-    def dir: Direction = {
-      requireIsHardware(target) // This has the side effect of calling _autoWrapPorts
-      target match {
-        case e: Element =>
-          DataMirror.directionOf(e) match {
-            case ActualDirection.Output => OUTPUT
-            case ActualDirection.Input  => INPUT
-            case _                      => NODIR
-          }
-        case _ => NODIR
-      }
-    }
-  }
-  implicit class cloneTypeable[T <: Data](target: T) {
-    import chisel3.experimental.DataMirror
-    def chiselCloneType: T = {
-      DataMirror.internal.chiselTypeClone(target).asInstanceOf[T]
-    }
-  }
-
-  type ChiselException = chisel3.internal.ChiselException
-
-  type Data = chisel3.Data
-  object Wire extends WireFactory {
-    import chisel3.CompileOptions
-
-    def apply[T <: Data](dummy: Int = 0, init: T)(implicit compileOptions: CompileOptions): T =
-      chisel3.WireDefault(init)
-
-    def apply[T <: Data](t: T, init: T)(implicit compileOptions: CompileOptions): T =
-      chisel3.WireDefault(t, init)
-  }
-  object Clock {
-    def apply(): Clock = new Clock
-
-    def apply(dir: Direction): Clock = {
-      val result = apply()
-      dir match {
-        case INPUT  => Input(result)
-        case OUTPUT => Output(result)
-        case _      => result
-      }
-    }
-  }
-  type Clock = chisel3.Clock
-
-  // Implicit conversion to allow fromBits because it's being deprecated in chisel3
-  implicit class fromBitsable[T <: Data](data: T) {
-    import chisel3.CompileOptions
-    import chisel3.internal.sourceinfo.SourceInfo
-
-    /** Creates an new instance of this type, unpacking the input Bits into
-      * structured data.
-      *
-      * This performs the inverse operation of toBits.
-      *
-      * @note does NOT assign to the object this is called on, instead creates
-      * and returns a NEW object (useful in a clone-and-assign scenario)
-      * @note does NOT check bit widths, may drop bits during assignment
-      * @note what fromBits assigs to must have known widths
-      */
-    def fromBits(that: Bits)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = {
-      that.asTypeOf(data)
-    }
-  }
-
-  type Aggregate = chisel3.Aggregate
-  object Vec extends chisel3.VecFactory {
-    import chisel3.CompileOptions
-    import chisel3.internal.sourceinfo._
-
-    @deprecated("Vec argument order should be size, t; this will be removed by the official release", "chisel3")
-    def apply[T <: Data](gen: T, n: Int)(implicit compileOptions: CompileOptions): Vec[T] =
-      apply(n, gen)
-
-    /** Creates a new [[Vec]] of length `n` composed of the result of the given
-      * function repeatedly applied.
-      *
-      * @param n   number of elements (and the number of times the function is
-      *            called)
-      * @param gen function that generates the [[Data]] that becomes the output
-      *            element
-      */
-    def fill[T <: Data](n: Int)(gen: => T)(implicit compileOptions: CompileOptions): Vec[T] =
-      apply(Seq.fill(n)(gen))
-
-    def apply[T <: Data](elts: Seq[T]): Vec[T] = macro VecTransform.apply_elts
-
-    /** @group SourceInfoTransformMacro */
-    def do_apply[T <: Data](elts: Seq[T])(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] =
-      chisel3.VecInit(elts)
-
-    def apply[T <: Data](elt0: T, elts: T*): Vec[T] = macro VecTransform.apply_elt0
-
-    /** @group SourceInfoTransformMacro */
-    def do_apply[T <: Data](
-      elt0: T,
-      elts: T*
-    )(
-      implicit sourceInfo: SourceInfo,
-      compileOptions:      CompileOptions
-    ): Vec[T] =
-      chisel3.VecInit(elt0 +: elts.toSeq)
-
-    def tabulate[T <: Data](n: Int)(gen: (Int) => T): Vec[T] = macro VecTransform.tabulate
-
-    /** @group SourceInfoTransformMacro */
-    def do_tabulate[T <: Data](
-      n:   Int
-    )(gen: (Int) => T
-    )(
-      implicit sourceInfo: SourceInfo,
-      compileOptions:      CompileOptions
-    ): Vec[T] =
-      chisel3.VecInit.tabulate(n)(gen)
-  }
-  type Vec[T <: Data] = chisel3.Vec[T]
-  type VecLike[T <: Data] = chisel3.VecLike[T]
-  type Record = chisel3.Record
-  type Bundle = chisel3.Bundle
-
-  val assert = chisel3.assert
-  val stop = chisel3.stop
-
-  /** This contains literal constructor factory methods that are deprecated as of Chisel3.
-    */
-  trait UIntFactory extends chisel3.UIntFactory {
-
-    /** Create a UInt literal with inferred width. */
-    def apply(n: String): UInt = n.asUInt
-
-    /** Create a UInt literal with fixed width. */
-    def apply(n: String, width: Int): UInt = n.asUInt(width.W)
-
-    /** Create a UInt literal with specified width. */
-    def apply(value: BigInt, width: Width): UInt = value.asUInt(width)
-
-    /** Create a UInt literal with fixed width. */
-    def apply(value: BigInt, width: Int): UInt = value.asUInt(width.W)
-
-    /** Create a UInt with a specified width - compatibility with Chisel2. */
-    // NOTE: This resolves UInt(width = 32)
-    def apply(dir: Option[Direction] = None, width: Int): UInt = apply(width.W)
-
-    /** Create a UInt literal with inferred width.- compatibility with Chisel2. */
-    def apply(value: BigInt): UInt = value.asUInt
-
-    /** Create a UInt with a specified direction and width - compatibility with Chisel2. */
-    def apply(dir: Direction, width: Int): UInt = apply(dir, width.W)
-
-    /** Create a UInt with a specified direction, but unspecified width - compatibility with Chisel2. */
-    def apply(dir: Direction): UInt = apply(dir, Width())
-    def apply(dir: Direction, width: Width): UInt = {
-      val result = apply(width)
-      dir match {
-        case INPUT  => Input(result)
-        case OUTPUT => Output(result)
-        case NODIR  => result
-      }
-    }
-
-    /** Create a UInt with a specified width */
-    def width(width: Int): UInt = apply(width.W)
-
-    /** Create a UInt port with specified width. */
-    def width(width: Width): UInt = apply(width)
-  }
-
-  /** This contains literal constructor factory methods that are deprecated as of Chisel3.
-    */
-  trait SIntFactory extends chisel3.SIntFactory {
-
-    /** Create a SInt type or port with fixed width. */
-    def width(width: Int): SInt = apply(width.W)
-
-    /** Create an SInt type with specified width. */
-    def width(width: Width): SInt = apply(width)
-
-    /** Create an SInt literal with inferred width. */
-    def apply(value: BigInt): SInt = value.asSInt
-
-    /** Create an SInt literal with fixed width. */
-    def apply(value: BigInt, width: Int): SInt = value.asSInt(width.W)
-
-    /** Create an SInt literal with specified width. */
-    def apply(value: BigInt, width: Width): SInt = value.asSInt(width)
-
-    def Lit(value: BigInt): SInt = value.asSInt
-    def Lit(value: BigInt, width: Int): SInt = value.asSInt(width.W)
-
-    /** Create a SInt with a specified width - compatibility with Chisel2. */
-    def apply(dir: Option[Direction] = None, width: Int): SInt = apply(width.W)
-
-    /** Create a SInt with a specified direction and width - compatibility with Chisel2. */
-    def apply(dir: Direction, width: Int): SInt = apply(dir, width.W)
-
-    /** Create a SInt with a specified direction, but unspecified width - compatibility with Chisel2. */
-    def apply(dir: Direction): SInt = apply(dir, Width())
-    def apply(dir: Direction, width: Width): SInt = {
-      val result = apply(width)
-      dir match {
-        case INPUT  => Input(result)
-        case OUTPUT => Output(result)
-        case NODIR  => result
-      }
-    }
-  }
-
-  /** This contains literal constructor factory methods that are deprecated as of Chisel3.
-    */
-  trait BoolFactory extends chisel3.BoolFactory {
-
-    /** Creates Bool literal.
-      */
-    def apply(x: Boolean): Bool = x.B
-
-    /** Create a UInt with a specified direction and width - compatibility with Chisel2. */
-    def apply(dir: Direction): Bool = {
-      val result = apply()
-      dir match {
-        case INPUT  => Input(result)
-        case OUTPUT => Output(result)
-        case NODIR  => result
-      }
-    }
-  }
-
-  type Element = chisel3.Element
-  type Bits = chisel3.Bits
-  object Bits extends UIntFactory
-  type Num[T <: Data] = chisel3.Num[T]
-  type UInt = chisel3.UInt
-  object UInt extends UIntFactory
-  type SInt = chisel3.SInt
-  object SInt extends SIntFactory
-  type Bool = chisel3.Bool
-  object Bool extends BoolFactory
-  val Mux = chisel3.Mux
-  type Reset = chisel3.Reset
-
-  implicit def resetToBool(reset: Reset): Bool = reset.asBool
-
-  type BlackBox = chisel3.internal.LegacyBlackBox
-
-  type MemBase[T <: Data] = chisel3.MemBase[T]
-
-  val Mem = chisel3.Mem
-  type Mem[T <: Data] = chisel3.Mem[T]
-
-  implicit class MemCompatibility(a: Mem.type) {
-    import chisel3.internal.sourceinfo.UnlocatableSourceInfo
-
-    def apply[T <: Data](t: T, size: BigInt)(implicit compileOptions: CompileOptions): Mem[T] =
-      a.do_apply(size, t)(UnlocatableSourceInfo, compileOptions)
-
-    def apply[T <: Data](t: T, size: Int)(implicit compileOptions: CompileOptions): Mem[T] =
-      a.do_apply(size, t)(UnlocatableSourceInfo, compileOptions)
-
-  }
-
-  val SeqMem = chisel3.SyncReadMem
-  type SeqMem[T <: Data] = chisel3.SyncReadMem[T]
-
-  implicit class SeqMemCompatibility(a: SeqMem.type) {
-    import chisel3.internal.sourceinfo.SourceInfo
-
-    def apply[T <: Data](
-      t:    T,
-      size: BigInt
-    )(
-      implicit sourceInfo: SourceInfo,
-      compileOptions:      CompileOptions
-    ): SyncReadMem[T] =
-      a.do_apply(size, t)
-
-    def apply[T <: Data](
-      t:    T,
-      size: Int
-    )(
-      implicit sourceInfo: SourceInfo,
-      compileOptions:      CompileOptions
-    ): SyncReadMem[T] =
-      a.do_apply(size, t)
-  }
-
-  import chisel3.CompileOptions
-
-  @deprecated("Use Chisel.Module", "Chisel 3.5")
-  type CompatibilityModule = chisel3.internal.LegacyModule
-  val Module = chisel3.Module
-  type Module = chisel3.internal.LegacyModule
-
-  val printf = chisel3.printf
-
-  val RegNext = chisel3.RegNext
-  val RegInit = chisel3.RegInit
-  object Reg {
-    import chisel3.CompileOptions
-    import chisel3.internal.sourceinfo.SourceInfo
-
-    // Passthrough for chisel3.Reg
-    // Single-element constructor to avoid issues caused by null default args in a type
-    // parameterized scope.
-    def apply[T <: Data](t: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T =
-      chisel3.Reg(t)
-
-    /** Creates a register with optional next and initialization values.
-      *
-      * @param t: data type for the register
-      * @param next: new value register is to be updated with every cycle (or
-      * empty to not update unless assigned to using the := operator)
-      * @param init: initialization value on reset (or empty for uninitialized,
-      * where the register value persists across a reset)
-      *
-      * @note this may result in a type error if called from a type parameterized
-      * function, since the Scala compiler isn't smart enough to know that null
-      * is a valid value. In those cases, you can either use the outType only Reg
-      * constructor or pass in `null.asInstanceOf[T]`.
-      */
-    def apply[T <: Data](
-      t:    T = null,
-      next: T = null,
-      init: T = null
-    )(
-      implicit sourceInfo: SourceInfo,
-      compileOptions:      CompileOptions
-    ): T = {
-      if (t ne null) {
-        val reg = if (init ne null) {
-          RegInit(t, init)
-        } else {
-          chisel3.Reg(t)
-        }
-        if (next ne null) {
-          reg := next
-        }
-        reg
-      } else if (next ne null) {
-        if (init ne null) {
-          RegNext(next, init)
-        } else {
-          RegNext(next)
-        }
-      } else if (init ne null) {
-        RegInit(init)
-      } else {
-        throwException("cannot infer type")
-      }
-    }
-  }
-
-  val when = chisel3.when
-  type WhenContext = chisel3.WhenContext
-
-  implicit class fromBigIntToLiteral(x: BigInt) extends chisel3.fromBigIntToLiteral(x)
-  implicit class fromtIntToLiteral(x: Int) extends chisel3.fromIntToLiteral(x)
-  implicit class fromtLongToLiteral(x: Long) extends chisel3.fromLongToLiteral(x)
-  implicit class fromStringToLiteral(x: String) extends chisel3.fromStringToLiteral(x)
-  implicit class fromBooleanToLiteral(x: Boolean) extends chisel3.fromBooleanToLiteral(x)
-  implicit class fromIntToWidth(x: Int) extends chisel3.fromIntToWidth(x)
-
-  @deprecated("Use object firrtl.util.BackendCompilationUtilities instead", "Chisel 3.5")
-  type BackendCompilationUtilities = chisel3.BackendCompilationUtilities
-  val ImplicitConversions = chisel3.util.ImplicitConversions
-
-  // Deprecated as of Chisel3
-  object chiselMain {
-    import java.io.File
-
-    private var target_dir: Option[String] = None
-
-    private def parseArgs(args: Array[String]): Unit = {
-      for (i <- args.indices) {
-        if (args(i) == "--targetDir") {
-          target_dir = Some(args(i + 1))
-        }
-      }
-    }
-
-    def apply[T <: Module](args: Array[String], gen: () => T): Unit =
-      Predef.assert(false, "No more chiselMain in Chisel3")
-
-    def run[T <: Module](args: Array[String], gen: () => T): Unit = {
-      val circuit = ChiselStage.elaborate(gen())
-      parseArgs(args)
-      val output_file = new File(target_dir.getOrElse(new File(".").getCanonicalPath) + "/" + circuit.name + ".fir")
-
-      (new phases.Emitter)
-        .transform(Seq(ChiselCircuitAnnotation(circuit), ChiselOutputFileAnnotation(output_file.toString)))
-    }
-  }
-
-  @deprecated("debug doesn't do anything in Chisel3 as no pruning happens in the frontend", "chisel3")
-  object debug {
-    def apply(arg: Data): Data = arg
-  }
-
-  // Deprecated as of Chsiel3
-  object throwException {
-    @throws(classOf[Exception])
-    def apply(s: String, t: Throwable = null): Nothing = {
-      val xcpt = new Exception(s, t)
-      throw xcpt
-    }
-  }
-
-  object testers {
-    type BasicTester = chisel3.testers.BasicTester
-    val TesterDriver = chisel3.testers.TesterDriver
-  }
-
-  val log2Ceil = chisel3.util.log2Ceil
-  val log2Floor = chisel3.util.log2Floor
-  val isPow2 = chisel3.util.isPow2
-
-  /** Compute the log2 rounded up with min value of 1 */
-  object log2Up {
-    def apply(in: BigInt): Int = {
-      require(in >= 0)
-      1.max((in - 1).bitLength)
-    }
-    def apply(in: Int): Int = apply(BigInt(in))
-  }
-
-  /** Compute the log2 rounded down with min value of 1 */
-  object log2Down {
-    def apply(in: BigInt): Int = log2Up(in) - (if (isPow2(in)) 0 else 1)
-    def apply(in: Int):    Int = apply(BigInt(in))
-  }
-
-  val BitPat = chisel3.util.BitPat
-  type BitPat = chisel3.util.BitPat
-
-  implicit class BitsObjectCompatibility(a: BitPat.type) {
-    def DC(width: Int): BitPat = a.dontCare(width)
-  }
-
-  type ArbiterIO[T <: Data] = chisel3.util.ArbiterIO[T]
-  type LockingArbiterLike[T <: Data] = chisel3.util.LockingArbiterLike[T]
-  type LockingRRArbiter[T <: Data] = chisel3.util.LockingRRArbiter[T]
-  type LockingArbiter[T <: Data] = chisel3.util.LockingArbiter[T]
-  type RRArbiter[T <: Data] = chisel3.util.RRArbiter[T]
-  type Arbiter[T <: Data] = chisel3.util.Arbiter[T]
-
-  val FillInterleaved = chisel3.util.FillInterleaved
-  val PopCount = chisel3.util.PopCount
-  val Fill = chisel3.util.Fill
-  val Reverse = chisel3.util.Reverse
-
-  val Cat = chisel3.util.Cat
-
-  val Log2 = chisel3.util.Log2
-
-  type SwitchContext[T <: Bits] = chisel3.util.SwitchContext[T]
-  val is = chisel3.util.is
-  val switch = chisel3.util.switch
-
-  type Counter = chisel3.util.Counter
-  val Counter = chisel3.util.Counter
-
-  type DecoupledIO[+T <: Data] = chisel3.util.DecoupledIO[T]
-  val DecoupledIO = chisel3.util.Decoupled
-  val Decoupled = chisel3.util.Decoupled
-  type QueueIO[T <: Data] = chisel3.util.QueueIO[T]
-
-  val Queue = chisel3.util.Queue
-  type Queue[T <: Data] = QueueCompatibility[T]
-
-  sealed class QueueCompatibility[T <: Data](
-    gen:     T,
-    entries: Int,
-    pipe:    Boolean = false,
-    flow:    Boolean = false
-  )(
-    implicit compileOptions: chisel3.CompileOptions)
-      extends chisel3.util.Queue[T](gen, entries, pipe, flow)(compileOptions) {
-
-    def this(gen: T, entries: Int, pipe: Boolean, flow: Boolean, override_reset: Option[Bool]) = {
-      this(gen, entries, pipe, flow)
-      this.override_reset = override_reset
-    }
-
-    def this(gen: T, entries: Int, pipe: Boolean, flow: Boolean, _reset: Bool) = {
-      this(gen, entries, pipe, flow)
-      this.override_reset = Some(_reset)
-    }
-
-  }
-
-  object Enum extends chisel3.util.Enum {
-
-    /** Returns n unique values of the specified type. Can be used with unpacking to define enums.
-      *
-      * nodeType must be of UInt type (note that Bits() creates a UInt) with unspecified width.
-      *
-      * @example {{{
-      * val state_on :: state_off :: Nil = Enum(UInt(), 2)
-      * val current_state = UInt()
-      * switch (current_state) {
-      *   is (state_on) {
-      *      ...
-      *   }
-      *   if (state_off) {
-      *      ...
-      *   }
-      * }
-      * }}}
-      */
-    def apply[T <: Bits](nodeType: T, n: Int): List[T] = {
-      require(nodeType.isInstanceOf[UInt], "Only UInt supported for enums")
-      require(!nodeType.widthKnown, "Bit width may no longer be specified for enums")
-      apply(n).asInstanceOf[List[T]]
-    }
-
-    /** An old Enum API that returns a map of symbols to UInts.
-      *
-      * Unlike the new list-based Enum, which can be unpacked into vals that the compiler
-      * understands and can check, map accesses can't be compile-time checked and typos may not be
-      * caught until runtime.
-      *
-      * Despite being deprecated, this is not to be removed from the compatibility layer API.
-      * Deprecation is only to nag users to do something safer.
-      */
-    @deprecated("Use list-based Enum", "not soon enough")
-    def apply[T <: Bits](nodeType: T, l: Symbol*): Map[Symbol, T] = {
-      require(nodeType.isInstanceOf[UInt], "Only UInt supported for enums")
-      require(!nodeType.widthKnown, "Bit width may no longer be specified for enums")
-      (l.zip(createValues(l.length))).toMap.asInstanceOf[Map[Symbol, T]]
-    }
-
-    /** An old Enum API that returns a map of symbols to UInts.
-      *
-      * Unlike the new list-based Enum, which can be unpacked into vals that the compiler
-      * understands and can check, map accesses can't be compile-time checked and typos may not be
-      * caught until runtime.
-      *
-      * Despite being deprecated, this is not to be removed from the compatibility layer API.
-      * Deprecation is only to nag users to do something safer.
-      */
-    @deprecated("Use list-based Enum", "not soon enough")
-    def apply[T <: Bits](nodeType: T, l: List[Symbol]): Map[Symbol, T] = {
-      require(nodeType.isInstanceOf[UInt], "Only UInt supported for enums")
-      require(!nodeType.widthKnown, "Bit width may no longer be specified for enums")
-      (l.zip(createValues(l.length))).toMap.asInstanceOf[Map[Symbol, T]]
-    }
-  }
-
-  /** LFSR16 generates a 16-bit linear feedback shift register, returning the register contents.
-    * This is useful for generating a pseudo-random sequence.
-    *
-    * The example below, taken from the unit tests, creates two 4-sided dice using `LFSR16` primitives:
-    * @example {{{
-    *   val bins = Reg(Vec(8, UInt(32.W)))
-    *
-    *   // Create two 4 sided dice and roll them each cycle.
-    *   // Use tap points on each LFSR so values are more independent
-    *   val die0 = Cat(Seq.tabulate(2) { i => LFSR16()(i) })
-    *   val die1 = Cat(Seq.tabulate(2) { i => LFSR16()(i + 2) })
-    *
-    *   val rollValue = die0 +& die1  // Note +& is critical because sum will need an extra bit.
-    *
-    *   bins(rollValue) := bins(rollValue) + 1.U
-    *
-    * }}}
-    */
-  object LFSR16 {
-
-    /** Generates a 16-bit linear feedback shift register, returning the register contents.
-      * @param increment optional control to gate when the LFSR updates.
-      */
-    def apply(increment: Bool = true.B): UInt =
-      VecInit(
-        FibonacciLFSR
-          .maxPeriod(16, increment, seed = Some(BigInt(1) << 15))
-          .asBools
-          .reverse
-      ).asUInt
-
-  }
-
-  val ListLookup = chisel3.util.ListLookup
-  val Lookup = chisel3.util.Lookup
-
-  val Mux1H = chisel3.util.Mux1H
-  val PriorityMux = chisel3.util.PriorityMux
-  val MuxLookup = chisel3.util.MuxLookup
-  val MuxCase = chisel3.util.MuxCase
-
-  val OHToUInt = chisel3.util.OHToUInt
-  val PriorityEncoder = chisel3.util.PriorityEncoder
-  val UIntToOH = chisel3.util.UIntToOH
-  val PriorityEncoderOH = chisel3.util.PriorityEncoderOH
-
-  val RegEnable = chisel3.util.RegEnable
-  val ShiftRegister = chisel3.util.ShiftRegister
-
-  type ValidIO[+T <: Data] = chisel3.util.Valid[T]
-  val Valid = chisel3.util.Valid
-  val Pipe = chisel3.util.Pipe
-  type Pipe[T <: Data] = chisel3.util.Pipe[T]
-
-  /** Package for experimental features, which may have their API changed, be removed, etc.
-    *
-    * Because its contents won't necessarily have the same level of stability and support as
-    * non-experimental, you must explicitly import this package to use its contents.
-    */
-  object experimental {
-    import scala.annotation.compileTimeOnly
-
-    class dump extends chisel3.internal.naming.dump
-    class treedump extends chisel3.internal.naming.treedump
-    class chiselName extends chisel3.internal.naming.chiselName
-  }
-
-  implicit class DataCompatibility(a: Data) {
-    import chisel3.internal.sourceinfo.DeprecatedSourceInfo
-
-    def toBits(implicit compileOptions: CompileOptions): UInt = a.do_asUInt(DeprecatedSourceInfo, compileOptions)
-
-  }
-
-  implicit class VecLikeCompatibility[T <: Data](a: VecLike[T]) {
-    import chisel3.internal.sourceinfo.DeprecatedSourceInfo
-
-    def read(idx: UInt)(implicit compileOptions: CompileOptions): T = a.do_apply(idx)(compileOptions)
-
-    def write(idx: UInt, data: T)(implicit compileOptions: CompileOptions): Unit =
-      a.do_apply(idx)(compileOptions).:=(data)(DeprecatedSourceInfo, compileOptions)
-
-  }
-
-  implicit class BitsCompatibility(a: Bits) {
-    import chisel3.internal.sourceinfo.DeprecatedSourceInfo
-
-    final def asBits(implicit compileOptions: CompileOptions): Bits = a.do_asUInt(DeprecatedSourceInfo, compileOptions)
-
-    final def toSInt(implicit compileOptions: CompileOptions): SInt = a.do_asSInt(DeprecatedSourceInfo, compileOptions)
-
-    final def toUInt(implicit compileOptions: CompileOptions): UInt = a.do_asUInt(DeprecatedSourceInfo, compileOptions)
-
-    final def toBools(implicit compileOptions: CompileOptions): Seq[Bool] =
-      a.do_asBools(DeprecatedSourceInfo, compileOptions)
-  }
-
-}
diff --git a/src/main/scala/chisel3/experimental/conversions/package.scala b/src/main/scala/chisel3/experimental/conversions/package.scala
deleted file mode 100644
index 7374f223..00000000
--- a/src/main/scala/chisel3/experimental/conversions/package.scala
+++ /dev/null
@@ -1,240 +0,0 @@
-package chisel3.experimental
-
-import chisel3._
-import chisel3.experimental.dataview._
-import scala.language.implicitConversions
-
-/** Implicit conversions from some Scala standard library types and [[Data]]
-  *
-  * @note As this leans heavily on the experimental [[DataView]] feature, these APIs are experimental and subject to change
-  */
-package object conversions {
-
-  /** Implicit conversion between `Seq` and `Vec` */
-  implicit def seq2vec[A: DataProduct, B <: Data](xs: Seq[A])(implicit dv: DataView[A, B]): Vec[B] =
-    xs.viewAs[Vec[B]]
-
-  /** Implicit conversion between [[Tuple2]] and [[HWTuple2]] */
-  implicit def tuple2hwtuple[T1: DataProduct, T2: DataProduct, V1 <: Data, V2 <: Data](
-    tup: (T1, T2)
-  )(
-    implicit v1: DataView[T1, V1],
-    v2:          DataView[T2, V2]
-  ): HWTuple2[V1, V2] = {
-    tup.viewAs[HWTuple2[V1, V2]]
-  }
-
-  /** Implicit conversion between [[Tuple3]] and [[HWTuple3]] */
-  implicit def tuple3hwtuple[T1: DataProduct, T2: DataProduct, T3: DataProduct, V1 <: Data, V2 <: Data, V3 <: Data](
-    tup: (T1, T2, T3)
-  )(
-    implicit v1: DataView[T1, V1],
-    v2:          DataView[T2, V2],
-    v3:          DataView[T3, V3]
-  ): HWTuple3[V1, V2, V3] = {
-    tup.viewAs[HWTuple3[V1, V2, V3]]
-  }
-
-  /** Implicit conversion between [[Tuple4]] and [[HWTuple4]] */
-  implicit def tuple4hwtuple[
-    T1: DataProduct,
-    T2: DataProduct,
-    T3: DataProduct,
-    T4: DataProduct,
-    V1 <: Data,
-    V2 <: Data,
-    V3 <: Data,
-    V4 <: Data
-  ](tup: (T1, T2, T3, T4)
-  )(
-    implicit v1: DataView[T1, V1],
-    v2:          DataView[T2, V2],
-    v3:          DataView[T3, V3],
-    v4:          DataView[T4, V4]
-  ): HWTuple4[V1, V2, V3, V4] = {
-    tup.viewAs[HWTuple4[V1, V2, V3, V4]]
-  }
-
-  /** Implicit conversion between [[Tuple5]] and [[HWTuple5]] */
-  implicit def tuple5hwtuple[
-    T1: DataProduct,
-    T2: DataProduct,
-    T3: DataProduct,
-    T4: DataProduct,
-    T5: DataProduct,
-    V1 <: Data,
-    V2 <: Data,
-    V3 <: Data,
-    V4 <: Data,
-    V5 <: Data
-  ](tup: (T1, T2, T3, T4, T5)
-  )(
-    implicit v1: DataView[T1, V1],
-    v2:          DataView[T2, V2],
-    v3:          DataView[T3, V3],
-    v4:          DataView[T4, V4],
-    v5:          DataView[T5, V5]
-  ): HWTuple5[V1, V2, V3, V4, V5] = {
-    tup.viewAs[HWTuple5[V1, V2, V3, V4, V5]]
-  }
-
-  /** Implicit conversion between [[Tuple6]] and [[HWTuple6]] */
-  implicit def tuple6hwtuple[
-    T1: DataProduct,
-    T2: DataProduct,
-    T3: DataProduct,
-    T4: DataProduct,
-    T5: DataProduct,
-    T6: DataProduct,
-    V1 <: Data,
-    V2 <: Data,
-    V3 <: Data,
-    V4 <: Data,
-    V5 <: Data,
-    V6 <: Data
-  ](tup: (T1, T2, T3, T4, T5, T6)
-  )(
-    implicit v1: DataView[T1, V1],
-    v2:          DataView[T2, V2],
-    v3:          DataView[T3, V3],
-    v4:          DataView[T4, V4],
-    v5:          DataView[T5, V5],
-    v6:          DataView[T6, V6]
-  ): HWTuple6[V1, V2, V3, V4, V5, V6] = {
-    tup.viewAs[HWTuple6[V1, V2, V3, V4, V5, V6]]
-  }
-
-  /** Implicit conversion between [[Tuple7]] and [[HWTuple7]] */
-  implicit def tuple7hwtuple[
-    T1: DataProduct,
-    T2: DataProduct,
-    T3: DataProduct,
-    T4: DataProduct,
-    T5: DataProduct,
-    T6: DataProduct,
-    T7: DataProduct,
-    V1 <: Data,
-    V2 <: Data,
-    V3 <: Data,
-    V4 <: Data,
-    V5 <: Data,
-    V6 <: Data,
-    V7 <: Data
-  ](tup: (T1, T2, T3, T4, T5, T6, T7)
-  )(
-    implicit v1: DataView[T1, V1],
-    v2:          DataView[T2, V2],
-    v3:          DataView[T3, V3],
-    v4:          DataView[T4, V4],
-    v5:          DataView[T5, V5],
-    v6:          DataView[T6, V6],
-    v7:          DataView[T7, V7]
-  ): HWTuple7[V1, V2, V3, V4, V5, V6, V7] = {
-    tup.viewAs[HWTuple7[V1, V2, V3, V4, V5, V6, V7]]
-  }
-
-  /** Implicit conversion between [[Tuple8]] and [[HWTuple8]] */
-  implicit def tuple8hwtuple[
-    T1: DataProduct,
-    T2: DataProduct,
-    T3: DataProduct,
-    T4: DataProduct,
-    T5: DataProduct,
-    T6: DataProduct,
-    T7: DataProduct,
-    T8: DataProduct,
-    V1 <: Data,
-    V2 <: Data,
-    V3 <: Data,
-    V4 <: Data,
-    V5 <: Data,
-    V6 <: Data,
-    V7 <: Data,
-    V8 <: Data
-  ](tup: (T1, T2, T3, T4, T5, T6, T7, T8)
-  )(
-    implicit v1: DataView[T1, V1],
-    v2:          DataView[T2, V2],
-    v3:          DataView[T3, V3],
-    v4:          DataView[T4, V4],
-    v5:          DataView[T5, V5],
-    v6:          DataView[T6, V6],
-    v7:          DataView[T7, V7],
-    v8:          DataView[T8, V8]
-  ): HWTuple8[V1, V2, V3, V4, V5, V6, V7, V8] = {
-    tup.viewAs[HWTuple8[V1, V2, V3, V4, V5, V6, V7, V8]]
-  }
-
-  /** Implicit conversion between [[Tuple9]] and [[HWTuple9]] */
-  implicit def tuple9hwtuple[
-    T1: DataProduct,
-    T2: DataProduct,
-    T3: DataProduct,
-    T4: DataProduct,
-    T5: DataProduct,
-    T6: DataProduct,
-    T7: DataProduct,
-    T8: DataProduct,
-    T9: DataProduct,
-    V1 <: Data,
-    V2 <: Data,
-    V3 <: Data,
-    V4 <: Data,
-    V5 <: Data,
-    V6 <: Data,
-    V7 <: Data,
-    V8 <: Data,
-    V9 <: Data
-  ](tup: (T1, T2, T3, T4, T5, T6, T7, T8, T9)
-  )(
-    implicit v1: DataView[T1, V1],
-    v2:          DataView[T2, V2],
-    v3:          DataView[T3, V3],
-    v4:          DataView[T4, V4],
-    v5:          DataView[T5, V5],
-    v6:          DataView[T6, V6],
-    v7:          DataView[T7, V7],
-    v8:          DataView[T8, V8],
-    v9:          DataView[T9, V9]
-  ): HWTuple9[V1, V2, V3, V4, V5, V6, V7, V8, V9] = {
-    tup.viewAs[HWTuple9[V1, V2, V3, V4, V5, V6, V7, V8, V9]]
-  }
-
-  /** Implicit conversion between [[Tuple10]] and [[HWTuple10]] */
-  implicit def tuple10hwtuple[
-    T1:  DataProduct,
-    T2:  DataProduct,
-    T3:  DataProduct,
-    T4:  DataProduct,
-    T5:  DataProduct,
-    T6:  DataProduct,
-    T7:  DataProduct,
-    T8:  DataProduct,
-    T9:  DataProduct,
-    T10: DataProduct,
-    V1 <: Data,
-    V2 <: Data,
-    V3 <: Data,
-    V4 <: Data,
-    V5 <: Data,
-    V6 <: Data,
-    V7 <: Data,
-    V8 <: Data,
-    V9 <: Data,
-    V10 <: Data
-  ](tup: (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10)
-  )(
-    implicit v1: DataView[T1, V1],
-    v2:          DataView[T2, V2],
-    v3:          DataView[T3, V3],
-    v4:          DataView[T4, V4],
-    v5:          DataView[T5, V5],
-    v6:          DataView[T6, V6],
-    v7:          DataView[T7, V7],
-    v8:          DataView[T8, V8],
-    v9:          DataView[T9, V9],
-    v10:         DataView[T10, V10]
-  ): HWTuple10[V1, V2, V3, V4, V5, V6, V7, V8, V9, V10] = {
-    tup.viewAs[HWTuple10[V1, V2, V3, V4, V5, V6, V7, V8, V9, V10]]
-  }
-}
diff --git a/src/main/scala/chisel3/stage/ChiselPhase.scala b/src/main/scala/chisel3/stage/ChiselPhase.scala
index 6c7affbc..050ba8fa 100644
--- a/src/main/scala/chisel3/stage/ChiselPhase.scala
+++ b/src/main/scala/chisel3/stage/ChiselPhase.scala
@@ -18,7 +18,6 @@ private[chisel3] object ChiselPhase {
       Dependency[chisel3.stage.phases.Checks],
       Dependency[chisel3.stage.phases.AddImplicitOutputFile],
       Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile],
-      Dependency[chisel3.stage.phases.MaybeAspectPhase],
       Dependency[chisel3.stage.phases.AddSerializationAnnotations],
       Dependency[chisel3.stage.phases.Convert],
       Dependency[chisel3.stage.phases.MaybeFirrtlStage]
diff --git a/src/main/scala/chisel3/stage/ChiselStage.scala b/src/main/scala/chisel3/stage/ChiselStage.scala
index 1224a8f1..2d4f26b0 100644
--- a/src/main/scala/chisel3/stage/ChiselStage.scala
+++ b/src/main/scala/chisel3/stage/ChiselStage.scala
@@ -158,7 +158,6 @@ object ChiselStage {
         Dependency[chisel3.stage.phases.Elaborate],
         Dependency[chisel3.stage.phases.AddImplicitOutputFile],
         Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile],
-        Dependency[chisel3.stage.phases.MaybeAspectPhase],
         Dependency[chisel3.stage.phases.Convert]
       )
     }
@@ -179,7 +178,6 @@ object ChiselStage {
       override val targets = Seq(
         Dependency[chisel3.stage.phases.AddImplicitOutputFile],
         Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile],
-        Dependency[chisel3.stage.phases.MaybeAspectPhase],
         Dependency[chisel3.stage.phases.Convert]
       )
     }
@@ -207,7 +205,6 @@ object ChiselStage {
         Dependency[chisel3.stage.phases.Elaborate],
         Dependency[chisel3.stage.phases.AddImplicitOutputFile],
         Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile],
-        Dependency[chisel3.stage.phases.MaybeAspectPhase],
         Dependency[chisel3.stage.phases.Convert],
         Dependency[firrtl.stage.phases.Compiler]
       )
@@ -233,7 +230,6 @@ object ChiselStage {
         Dependency[chisel3.stage.phases.Elaborate],
         Dependency[chisel3.stage.phases.AddImplicitOutputFile],
         Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile],
-        Dependency[chisel3.stage.phases.MaybeAspectPhase],
         Dependency[chisel3.stage.phases.Convert],
         Dependency[firrtl.stage.phases.Compiler]
       )
@@ -258,7 +254,6 @@ object ChiselStage {
         Dependency[chisel3.stage.phases.Elaborate],
         Dependency[chisel3.stage.phases.AddImplicitOutputFile],
         Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile],
-        Dependency[chisel3.stage.phases.MaybeAspectPhase],
         Dependency[chisel3.stage.phases.Convert],
         Dependency[firrtl.stage.phases.Compiler]
       )
diff --git a/src/main/scala/chisel3/stage/phases/AspectPhase.scala b/src/main/scala/chisel3/stage/phases/AspectPhase.scala
deleted file mode 100644
index efe2c3a4..00000000
--- a/src/main/scala/chisel3/stage/phases/AspectPhase.scala
+++ /dev/null
@@ -1,36 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chisel3.stage.phases
-
-import chisel3.aop.Aspect
-import chisel3.RawModule
-import chisel3.stage.DesignAnnotation
-import firrtl.AnnotationSeq
-import firrtl.options.Phase
-
-import scala.collection.mutable
-
-/** Phase that consumes all Aspects and calls their toAnnotationSeq methods.
-  *
-  * Consumes the [[chisel3.stage.DesignAnnotation]] and converts every [[Aspect]] into their annotations prior to executing FIRRTL
-  */
-class AspectPhase extends Phase {
-  def transform(annotations: AnnotationSeq): AnnotationSeq = {
-    var dut: Option[RawModule] = None
-    val aspects = mutable.ArrayBuffer[Aspect[_]]()
-
-    val remainingAnnotations = annotations.flatMap {
-      case DesignAnnotation(d) =>
-        dut = Some(d)
-        Nil
-      case a: Aspect[_] =>
-        aspects += a
-        Nil
-      case other => Seq(other)
-    }
-    if (dut.isDefined) {
-      val newAnnotations = aspects.flatMap { _.resolveAspect(dut.get, remainingAnnotations) }
-      remainingAnnotations ++ newAnnotations
-    } else annotations
-  }
-}
diff --git a/src/main/scala/chisel3/stage/phases/Emitter.scala b/src/main/scala/chisel3/stage/phases/Emitter.scala
index 254f8add..67bb1486 100644
--- a/src/main/scala/chisel3/stage/phases/Emitter.scala
+++ b/src/main/scala/chisel3/stage/phases/Emitter.scala
@@ -29,7 +29,6 @@ class Emitter extends Phase {
       Dependency[Elaborate],
       Dependency[AddImplicitOutputFile],
       Dependency[AddImplicitOutputAnnotationFile],
-      Dependency[MaybeAspectPhase]
     )
   override def optionalPrerequisites = Seq.empty
   override def optionalPrerequisiteOf = Seq(Dependency[Convert])
diff --git a/src/main/scala/chisel3/stage/phases/MaybeAspectPhase.scala b/src/main/scala/chisel3/stage/phases/MaybeAspectPhase.scala
deleted file mode 100644
index dcd0dfe0..00000000
--- a/src/main/scala/chisel3/stage/phases/MaybeAspectPhase.scala
+++ /dev/null
@@ -1,23 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chisel3.stage.phases
-
-import chisel3.aop.Aspect
-import firrtl.AnnotationSeq
-import firrtl.options.{Dependency, Phase}
-
-/** Run [[AspectPhase]] if a [[chisel3.aop.Aspect]] is present.
-  */
-class MaybeAspectPhase extends Phase {
-
-  override def prerequisites = Seq(Dependency[Elaborate])
-  override def optionalPrerequisites = Seq.empty
-  override def optionalPrerequisiteOf = Seq.empty
-  override def invalidates(a: Phase) = false
-
-  def transform(annotations: AnnotationSeq): AnnotationSeq = {
-    if (annotations.collectFirst { case a: Aspect[_] => annotations }.isDefined) {
-      new AspectPhase().transform(annotations)
-    } else annotations
-  }
-}
diff --git a/src/main/scala/chisel3/util/BlackBoxUtils.scala b/src/main/scala/chisel3/util/BlackBoxUtils.scala
deleted file mode 100644
index 579a6307..00000000
--- a/src/main/scala/chisel3/util/BlackBoxUtils.scala
+++ /dev/null
@@ -1,89 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chisel3.util
-
-import chisel3._
-import chisel3.experimental.{ChiselAnnotation, RunFirrtlTransform}
-import firrtl.transforms.{BlackBoxInlineAnno, BlackBoxNotFoundException, BlackBoxPathAnno, BlackBoxSourceHelper}
-import firrtl.annotations.ModuleName
-import logger.LazyLogging
-
-private[util] object BlackBoxHelpers {
-
-  implicit class BlackBoxInlineAnnoHelpers(anno: BlackBoxInlineAnno.type) extends LazyLogging {
-
-    /** Generate a BlackBoxInlineAnno from a Java Resource and a module name. */
-    def fromResource(resourceName: String, moduleName: ModuleName) = try {
-      val blackBoxFile = os.resource / os.RelPath(resourceName.dropWhile(_ == '/'))
-      val contents = os.read(blackBoxFile)
-      if (contents.size > BigInt(2).pow(20)) {
-        val message =
-          s"Black box resource $resourceName, which will be converted to an inline annotation, is greater than 1 MiB." +
-            "This may affect compiler performance. Consider including this resource via a black box path."
-        logger.warn(message)
-      }
-      BlackBoxInlineAnno(moduleName, blackBoxFile.last, contents)
-    } catch {
-      case e: os.ResourceNotFoundException =>
-        throw new BlackBoxNotFoundException(resourceName, e.getMessage)
-    }
-  }
-}
-
-import BlackBoxHelpers._
-
-trait HasBlackBoxResource extends BlackBox {
-  self: BlackBox =>
-
-  /** Copies a Java resource containing some text into the output directory. This is typically used to copy a Verilog file
-    * to the final output directory, but may be used to copy any Java resource (e.g., a C++ testbench).
-    *
-    * Resource files are located in project_root/src/main/resources/.
-    * Example of adding the resource file project_root/src/main/resources/blackbox.v:
-    * {{{
-    * addResource("/blackbox.v")
-    * }}}
-    */
-  def addResource(blackBoxResource: String): Unit = {
-    val anno = new ChiselAnnotation with RunFirrtlTransform {
-      def toFirrtl = BlackBoxInlineAnno.fromResource(blackBoxResource, self.toNamed)
-      def transformClass = classOf[BlackBoxSourceHelper]
-    }
-    chisel3.experimental.annotate(anno)
-  }
-}
-
-trait HasBlackBoxInline extends BlackBox {
-  self: BlackBox =>
-
-  /** Creates a black box verilog file, from the contents of a local string
-    *
-    * @param blackBoxName   The black box module name, to create filename
-    * @param blackBoxInline The black box contents
-    */
-  def setInline(blackBoxName: String, blackBoxInline: String): Unit = {
-    val anno = new ChiselAnnotation with RunFirrtlTransform {
-      def toFirrtl = BlackBoxInlineAnno(self.toNamed, blackBoxName, blackBoxInline)
-      def transformClass = classOf[BlackBoxSourceHelper]
-    }
-    chisel3.experimental.annotate(anno)
-  }
-}
-
-trait HasBlackBoxPath extends BlackBox {
-  self: BlackBox =>
-
-  /** Copies a file to the target directory
-    *
-    * This works with absolute and relative paths. Relative paths are relative
-    * to the current working directory, which is generally not the same as the
-    * target directory.
-    */
-  def addPath(blackBoxPath: String): Unit = {
-    val anno = new ChiselAnnotation with RunFirrtlTransform {
-      def toFirrtl = BlackBoxPathAnno(self.toNamed, blackBoxPath)
-      def transformClass = classOf[BlackBoxSourceHelper]
-    }
-    chisel3.experimental.annotate(anno)
-  }
-}
diff --git a/src/main/scala/chisel3/util/ExtModuleUtils.scala b/src/main/scala/chisel3/util/ExtModuleUtils.scala
deleted file mode 100644
index 8a687d36..00000000
--- a/src/main/scala/chisel3/util/ExtModuleUtils.scala
+++ /dev/null
@@ -1,63 +0,0 @@
-// See LICENSE for license details.
-
-package chisel3.util
-
-import chisel3.experimental.{ChiselAnnotation, ExtModule, RunFirrtlTransform}
-import firrtl.transforms.{BlackBoxInlineAnno, BlackBoxNotFoundException, BlackBoxPathAnno, BlackBoxSourceHelper}
-
-import BlackBoxHelpers._
-
-trait HasExtModuleResource extends ExtModule {
-  self: ExtModule =>
-
-  /** Copies a resource file to the target directory
-    *
-    * Resource files are located in project_root/src/main/resources/.
-    * Example of adding the resource file project_root/src/main/resources/blackbox.v:
-    * {{{
-    * addResource("/blackbox.v")
-    * }}}
-    */
-  def addResource(blackBoxResource: String): Unit = {
-    val anno = new ChiselAnnotation with RunFirrtlTransform {
-      def toFirrtl = BlackBoxInlineAnno.fromResource(blackBoxResource, self.toNamed)
-      def transformClass = classOf[BlackBoxSourceHelper]
-    }
-    chisel3.experimental.annotate(anno)
-  }
-}
-
-trait HasExtModuleInline extends ExtModule {
-  self: ExtModule =>
-
-  /** Creates a black box verilog file, from the contents of a local string
-    *
-    * @param blackBoxName   The black box module name, to create filename
-    * @param blackBoxInline The black box contents
-    */
-  def setInline(blackBoxName: String, blackBoxInline: String): Unit = {
-    val anno = new ChiselAnnotation with RunFirrtlTransform {
-      def toFirrtl = BlackBoxInlineAnno(self.toNamed, blackBoxName, blackBoxInline)
-      def transformClass = classOf[BlackBoxSourceHelper]
-    }
-    chisel3.experimental.annotate(anno)
-  }
-}
-
-trait HasExtModulePath extends ExtModule {
-  self: ExtModule =>
-
-  /** Copies a file to the target directory
-    *
-    * This works with absolute and relative paths. Relative paths are relative
-    * to the current working directory, which is generally not the same as the
-    * target directory.
-    */
-  def addPath(blackBoxPath: String): Unit = {
-    val anno = new ChiselAnnotation with RunFirrtlTransform {
-      def toFirrtl = BlackBoxPathAnno(self.toNamed, blackBoxPath)
-      def transformClass = classOf[BlackBoxSourceHelper]
-    }
-    chisel3.experimental.annotate(anno)
-  }
-}
diff --git a/src/main/scala/chisel3/util/Math.scala b/src/main/scala/chisel3/util/Math.scala
index 6eab9241..1fc45650 100644
--- a/src/main/scala/chisel3/util/Math.scala
+++ b/src/main/scala/chisel3/util/Math.scala
@@ -23,11 +23,10 @@ import chisel3.internal
   * }}}
   */
 object log2Up {
-  // Do not deprecate until zero-width wires fully work:
-  // https://github.com/freechipsproject/chisel3/issues/847
-  //@chiselRuntimeDeprecated
-  //@deprecated("Use log2Ceil instead", "chisel3")
-  def apply(in: BigInt): Int = Chisel.log2Up(in)
+  def apply(in: BigInt): Int = {
+    require(in >= 0)
+    1.max((in - 1).bitLength)
+  }
 }
 
 /** Compute the log2 of a Scala integer, rounded up.
@@ -66,7 +65,7 @@ object log2Down {
   // https://github.com/freechipsproject/chisel3/issues/847
   //@chiselRuntimeDeprecated
   //@deprecated("Use log2Floor instead", "chisel3")
-  def apply(in: BigInt): Int = Chisel.log2Down(in)
+  def apply(in: BigInt): Int = log2Up(in) - (if (isPow2(in)) 0 else 1)
 }
 
 /** Compute the log2 of a Scala integer, rounded down.