diff options
| author | Andrew Waterman | 2015-07-30 17:35:04 -0700 |
|---|---|---|
| committer | Andrew Waterman | 2015-07-30 17:35:04 -0700 |
| commit | 2b9b7d3bf58a96b5cb79bbcb1578031e1db953ea (patch) | |
| tree | 1cebe6d9cb96fa64713388ad49d7486e6d36d703 /src/main/scala | |
| parent | cf96506fd026cafee86f546fbe14ef9749f15642 (diff) | |
Add missing Wire()
Diffstat (limited to 'src/main/scala')
| -rw-r--r-- | src/main/scala/Chisel/utils.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/utils.scala b/src/main/scala/Chisel/utils.scala index e3aff994..f1c5e484 100644 --- a/src/main/scala/Chisel/utils.scala +++ b/src/main/scala/Chisel/utils.scala @@ -530,7 +530,7 @@ object Pipe { def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int): ValidIO[T] = { if (latency == 0) { - val out = Valid(enqBits) + val out = Wire(Valid(enqBits)) out.valid <> enqValid out.bits <> enqBits out |