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authorJim Lawson2020-01-07 14:31:42 -0800
committerGitHub2020-01-07 14:31:42 -0800
commitce82ffaaeb2301af756b032c01e879e700299ea1 (patch)
tree4e10201d02d43c560a8f22aae3263e6edfd63d0e /src/main/scala/chisel3
parentc720c99a75f565c8b4fbc7147d7b9daee9123d10 (diff)
parentd4300b9deae6dde7ce0f314ea73a9ca4a1c3868c (diff)
Merge branch 'master' into fix-bitpat-whitespace
Diffstat (limited to 'src/main/scala/chisel3')
-rw-r--r--src/main/scala/chisel3/stage/package.scala1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/stage/package.scala b/src/main/scala/chisel3/stage/package.scala
index 67d38ae7..57766be6 100644
--- a/src/main/scala/chisel3/stage/package.scala
+++ b/src/main/scala/chisel3/stage/package.scala
@@ -28,7 +28,6 @@ package object stage {
private[chisel3] implicit object ChiselExecutionResultView extends OptionsView[ChiselExecutionResult] {
- lazy val dummyWriteEmitted = new firrtl.stage.phases.WriteEmitted
lazy val dummyConvert = new Convert
lazy val dummyEmitter = new Emitter