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| author | Jim Lawson | 2017-03-13 11:39:21 -1000 |
|---|---|---|
| committer | Richard Lin | 2017-03-13 14:39:21 -0700 |
| commit | a6798adbf7567cf105f8190ebd293a4cfb3aeb11 (patch) | |
| tree | 0a66072a06f9ba5bf4ccd56c6d0b6db28b53152d /src/main/scala/chisel3 | |
| parent | a290d77ef3e88b200ab61cd41fcd1a1138321b66 (diff) | |
Revert "Change Vec creation to check if gen is lit (and hence needs t… (#530)
* Revert "Change Vec creation to check if gen is lit (and hence needs to be declared)"
This reverts commit dc86e7e1734d6abacb739b488df1de231e6b41b2.
This may address #522 - using chiselCloneType (instead of cloneType) to preserve directionality.
* Add missing implicits to Vec.apply() signature.
* Use correct macro (CompileOptionsTransform) for indexWhere.
Diffstat (limited to 'src/main/scala/chisel3')
0 files changed, 0 insertions, 0 deletions