diff options
| author | Ruige Lee | 2021-08-22 00:08:54 +0800 |
|---|---|---|
| committer | GitHub | 2021-08-21 16:08:54 +0000 |
| commit | a3d51e4c91059362b20296eaa00f06f96ec7a4e1 (patch) | |
| tree | 126f13c6232952718762f26e0f81348d7dac0de2 /src/main/scala/chisel3 | |
| parent | efe448c5ca907b3d7a40407f720aa6d4ff2a1a4e (diff) | |
Update ChiselStage.scala (#2082)
There might be some "@"?
Diffstat (limited to 'src/main/scala/chisel3')
| -rw-r--r-- | src/main/scala/chisel3/stage/ChiselStage.scala | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/main/scala/chisel3/stage/ChiselStage.scala b/src/main/scala/chisel3/stage/ChiselStage.scala index 989b3a17..0c76f411 100644 --- a/src/main/scala/chisel3/stage/ChiselStage.scala +++ b/src/main/scala/chisel3/stage/ChiselStage.scala @@ -47,7 +47,7 @@ class ChiselStage extends Stage { /** Convert a Chisel module to a CHIRRTL string * @param gen a call-by-name Chisel module * @param args additional command line arguments to pass to Chisel - * param annotations additional annotations to pass to Chisel + * @param annotations additional annotations to pass to Chisel * @return a string containing the Verilog output */ final def emitChirrtl( @@ -70,7 +70,7 @@ class ChiselStage extends Stage { /** Convert a Chisel module to a FIRRTL string * @param gen a call-by-name Chisel module * @param args additional command line arguments to pass to Chisel - * param annotations additional annotations to pass to Chisel + * @param annotations additional annotations to pass to Chisel * @return a string containing the FIRRTL output */ final def emitFirrtl( @@ -90,7 +90,7 @@ class ChiselStage extends Stage { /** Convert a Chisel module to Verilog * @param gen a call-by-name Chisel module * @param args additional command line arguments to pass to Chisel - * param annotations additional annotations to pass to Chisel + * @param annotations additional annotations to pass to Chisel * @return a string containing the Verilog output */ final def emitVerilog( @@ -110,7 +110,7 @@ class ChiselStage extends Stage { /** Convert a Chisel module to SystemVerilog * @param gen a call-by-name Chisel module * @param args additional command line arguments to pass to Chisel - * param annotations additional annotations to pass to Chisel + * @param annotations additional annotations to pass to Chisel * @return a string containing the SystemVerilog output */ final def emitSystemVerilog( |