Decouple implementation details from LoadMemoryAnnotation. (#1034)

1 files changed, 5 insertions, 1 deletions

diff --git a/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala b/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
index e8967601..5e78fa34 100644
--- a/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
+++ b/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
@@ -168,6 +168,10 @@ class LoadMemoryTransform extends Transform {
         memoryAnnotations.get(fullMemoryName) match {
           case Some(lma @ LoadMemoryAnnotation(ComponentName(componentName, moduleName), _, hexOrBinary, _)) =>
             val writer = new java.io.StringWriter
+            val readmem = hexOrBinary match {
+              case MemoryLoadFileType.Binary => "$readmemb"
+              case MemoryLoadFileType.Hex => "$readmemh"
+            }
 
             modulesByName.get(moduleName.name).foreach { module =>
                 val renderer = verilogEmitter.getRenderer(module, modulesByName)(writer)
@@ -178,7 +182,7 @@ class LoadMemoryTransform extends Transform {
                 renderer.emitVerilogBind(bindsToName,
                   s"""
                      |initial begin
-                     |  $$readmem$hexOrBinary("$loadFileName", ${myModule.name}.$componentName);
+                     |  $readmem("$loadFileName", ${myModule.name}.$componentName);
                      |end
                       """.stripMargin)
                 val inLineText = writer.toString + "\n" +