diff options
| author | ducky | 2016-11-16 15:23:36 -0800 |
|---|---|---|
| committer | ducky | 2016-11-21 12:48:10 -0800 |
| commit | 876bc32feca6bd0a2aaec7019fd3d29675ce0255 (patch) | |
| tree | 9598426ff507c096340e37fcf9cd1e75f41e5318 /src/main/scala/chisel3 | |
| parent | 2db9bc81015000b5ee4581dc57c0f339ae9f9329 (diff) | |
Fix open-open range specifier, remove dead code, restyle tests
Diffstat (limited to 'src/main/scala/chisel3')
| -rw-r--r-- | src/main/scala/chisel3/package.scala | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala index 436534e1..b49f6dec 100644 --- a/src/main/scala/chisel3/package.scala +++ b/src/main/scala/chisel3/package.scala @@ -1,10 +1,9 @@ - // See LICENSE for license details. package object chisel3 { // scalastyle:ignore package.object.name import scala.language.experimental.macros - import internal.firrtl.Width + import internal.firrtl.{Width, NumericBound} import internal.sourceinfo.{SourceInfo, SourceInfoTransform} import util.BitPat @@ -12,8 +11,6 @@ package object chisel3 { // scalastyle:ignore package.object.name import chisel3.util._ import chisel3.internal.firrtl.Port - import chisel3.internal.firrtl.NumericBound - type Direction = chisel3.core.Direction val Input = chisel3.core.Input val Output = chisel3.core.Output |
