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authorJim Lawson2016-08-29 12:17:48 -0700
committerJim Lawson2016-08-29 12:17:48 -0700
commit6df3a785f8abe706838bc5b4b35c3374b6512f96 (patch)
treea6b4961f966b69577ff4de28f2aa770b9355b7d9 /src/main/scala/chisel3
parent5fcdd12fe92bd22f9cdfb8f5e39e510684b709bf (diff)
Pass compileOptions as an implicit Module parameter.
Diffstat (limited to 'src/main/scala/chisel3')
-rw-r--r--src/main/scala/chisel3/testers/BasicTester.scala3
-rw-r--r--src/main/scala/chisel3/util/Arbiter.scala1
-rw-r--r--src/main/scala/chisel3/util/Decoupled.scala1
-rw-r--r--src/main/scala/chisel3/util/Valid.scala1
4 files changed, 5 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/testers/BasicTester.scala b/src/main/scala/chisel3/testers/BasicTester.scala
index 329237c6..0c8df2eb 100644
--- a/src/main/scala/chisel3/testers/BasicTester.scala
+++ b/src/main/scala/chisel3/testers/BasicTester.scala
@@ -9,8 +9,9 @@ import internal._
import internal.Builder.pushCommand
import internal.firrtl._
import internal.sourceinfo.SourceInfo
+import chisel3.NotStrict.NotStrictCompileOptions
-class BasicTester extends Module {
+class BasicTester extends Module() {
// The testbench has no IOs, rather it should communicate using printf, assert, and stop.
val io = IO(new Bundle())
diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala
index 5875b3f2..57e81708 100644
--- a/src/main/scala/chisel3/util/Arbiter.scala
+++ b/src/main/scala/chisel3/util/Arbiter.scala
@@ -6,6 +6,7 @@
package chisel3.util
import chisel3._
+import chisel3.NotStrict.NotStrictCompileOptions
/** An I/O bundle for the Arbiter */
class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle {
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 42f58ea9..8064d19b 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -6,6 +6,7 @@
package chisel3.util
import chisel3._
+import chisel3.NotStrict.NotStrictCompileOptions
/** An I/O Bundle with simple handshaking using valid and ready signals for data 'bits'*/
class DecoupledIO[+T <: Data](gen: T) extends Bundle
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index 743038f3..d465d18d 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -6,6 +6,7 @@
package chisel3.util
import chisel3._
+import chisel3.NotStrict.NotStrictCompileOptions
/** An Bundle containing data and a signal determining if it is valid */
class Valid[+T <: Data](gen: T) extends Bundle