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| author | Abongwa Bonalais | 2021-11-03 06:46:49 +0100 |
|---|---|---|
| committer | GitHub | 2021-11-03 05:46:49 +0000 |
| commit | 614551236186d35ff42ea9c90130a3b80646ba69 (patch) | |
| tree | 5b87f54e5d09dc58016e38cdcfe1eaa364e61e78 /src/main/scala/chisel3 | |
| parent | a79f57565e7157d137628d1aaeae750f98e3d88b (diff) | |
Add field grouping ScalaDoc for ArbiterIO (#2208)
* Update Arbiter.scala
* Update src/main/scala/chisel3/util/Arbiter.scala
changed group name
Co-authored-by: Megan Wachs <megan@sifive.com>
* minor changes on grouping ArbiterIO
* removed unmatched closing brace
* Remove groupdesc from Arbiter.scala
* Added groupdesc to Aggregate.scala
* Update Arbiter.scala
* Update core/src/main/scala/chisel3/Aggregate.scala
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update Arbiter.scala
* Update src/main/scala/chisel3/util/Arbiter.scala
Added suugestions.
Co-authored-by: Megan Wachs <megan@sifive.com>
* added suggestions from review
* added suggestions from review
* Resolved conflicts
* update Arbiter.scala
* Update core/src/main/scala/chisel3/Aggregate.scala
deleted groudesc for ArbiterIO
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update Scaladoc syntax
* removed some lines
* Better documentation
* Removed @param and @gen
* Update core/src/main/scala/chisel3/Aggregate.scala
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update src/main/scala/chisel3/util/Arbiter.scala
Co-authored-by: Megan Wachs <megan@sifive.com>
* Added groupdesc to ArbiterIO
* Update src/main/scala/chisel3/util/Arbiter.scala
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update core/src/main/scala/chisel3/Aggregate.scala
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update Arbiter.scala
* Update src/main/scala/chisel3/util/Arbiter.scala
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update Arbiter.scala
Co-authored-by: Megan Wachs <megan@sifive.com>
Diffstat (limited to 'src/main/scala/chisel3')
| -rw-r--r-- | src/main/scala/chisel3/util/Arbiter.scala | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala index 135700fa..b68acae1 100644 --- a/src/main/scala/chisel3/util/Arbiter.scala +++ b/src/main/scala/chisel3/util/Arbiter.scala @@ -10,6 +10,7 @@ import chisel3.internal.naming.chiselName // can't use chisel3_ version because /** IO bundle definition for an Arbiter, which takes some number of ready-valid inputs and outputs * (selects) at most one. + * @groupdesc Signals The actual hardware fields of the Bundle * * @param gen data type * @param n number of inputs @@ -17,8 +18,20 @@ import chisel3.internal.naming.chiselName // can't use chisel3_ version because class ArbiterIO[T <: Data](private val gen: T, val n: Int) extends Bundle { // See github.com/freechipsproject/chisel3/issues/765 for why gen is a private val and proposed replacement APIs. +/** Input data, one per potential sender + * + * @group Signals + */ val in = Flipped(Vec(n, Decoupled(gen))) +/** Output data after arbitration + * + * @group Signals + */ val out = Decoupled(gen) +/** One-Hot vector indicating which output was chosen + * + * @group Signals + */ val chosen = Output(UInt(log2Ceil(n).W)) } |