diff options
| author | Richard Lin | 2019-03-21 18:21:07 -0700 |
|---|---|---|
| committer | edwardcwang | 2019-03-21 18:21:07 -0700 |
| commit | 5574131876d8bbe73cfcd3b5ae8a1317b60142c0 (patch) | |
| tree | 26ddddf647cf3ee1bb99c2eb72fd0d6296bd2557 /src/main/scala/chisel3 | |
| parent | 1183e98cfd0626f879177f693682c917f28e3d62 (diff) | |
Remove @chiselName from MixedVec (#1045)
Diffstat (limited to 'src/main/scala/chisel3')
| -rw-r--r-- | src/main/scala/chisel3/util/MixedVec.scala | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/util/MixedVec.scala b/src/main/scala/chisel3/util/MixedVec.scala index 80e224d3..9b70cd41 100644 --- a/src/main/scala/chisel3/util/MixedVec.scala +++ b/src/main/scala/chisel3/util/MixedVec.scala @@ -4,7 +4,6 @@ package chisel3.util import chisel3._ import chisel3.core.{Data, requireIsChiselType, requireIsHardware} -import chisel3.internal.naming.chiselName import scala.collection.immutable.ListMap @@ -86,7 +85,6 @@ object MixedVec { * v(2) := 101.U(32.W) * }}} */ -@chiselName final class MixedVec[T <: Data](private val eltsIn: Seq[T]) extends Record with collection.IndexedSeq[T] { // We want to create MixedVec only with Chisel types. if (compileOptions.declaredTypeMustBeUnbound) { |