summaryrefslogtreecommitdiff
path: root/src/main/scala/chisel3
diff options
context:
space:
mode:
authorducky2018-06-28 14:53:00 -0700
committerRichard Lin2018-07-04 18:39:28 -0500
commit4cf5caf86a072bc4af581536930469b82796dd27 (patch)
tree5f3e4f1b8dd2cfc268dfbc84b5edb856c6d02c3a /src/main/scala/chisel3
parent28261aefc081a9edfff1cd67d2a4a386933dcb4b (diff)
properly fix undefined clock/reset issues
Diffstat (limited to 'src/main/scala/chisel3')
-rw-r--r--src/main/scala/chisel3/testers/BasicTester.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/testers/BasicTester.scala b/src/main/scala/chisel3/testers/BasicTester.scala
index 7bb441ba..1f988a3b 100644
--- a/src/main/scala/chisel3/testers/BasicTester.scala
+++ b/src/main/scala/chisel3/testers/BasicTester.scala
@@ -26,7 +26,7 @@ class BasicTester extends Module() {
def stop()(implicit sourceInfo: SourceInfo) {
// TODO: rewrite this using library-style SourceInfo passing.
when (!reset.toBool) {
- pushCommand(Stop(sourceInfo, Node(clock), 0))
+ pushCommand(Stop(sourceInfo, clock.ref, 0))
}
}