diff options
| author | Jerry Zhao | 2021-03-01 11:39:33 -0800 |
|---|---|---|
| committer | GitHub | 2021-03-01 19:39:33 +0000 |
| commit | 43de37fdd48bcb6bbc861553715b06be3c67f6bf (patch) | |
| tree | 539d944b6daba6e0e5ba1a14912db1046ad6ef7b /src/main/scala/chisel3 | |
| parent | 923ccbde1353e37f0948d3c5d94b49965dc6d950 (diff) | |
Fix conversions between DecoupledIO and IrrevocableIO (#1781)
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Diffstat (limited to 'src/main/scala/chisel3')
| -rw-r--r-- | src/main/scala/chisel3/util/Decoupled.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index 006001ec..33682020 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -108,7 +108,7 @@ object Decoupled @chiselName def apply[T <: Data](irr: IrrevocableIO[T]): DecoupledIO[T] = { require(DataMirror.directionOf(irr.bits) == Direction.Output, "Only safe to cast produced Irrevocable bits to Decoupled.") - val d = Wire(new DecoupledIO(irr.bits)) + val d = Wire(new DecoupledIO(chiselTypeOf(irr.bits))) d.bits := irr.bits d.valid := irr.valid irr.ready := d.ready @@ -139,7 +139,7 @@ object Irrevocable */ def apply[T <: Data](dec: DecoupledIO[T]): IrrevocableIO[T] = { require(DataMirror.directionOf(dec.bits) == Direction.Input, "Only safe to cast consumed Decoupled bits to Irrevocable.") - val i = Wire(new IrrevocableIO(dec.bits)) + val i = Wire(new IrrevocableIO(chiselTypeOf(dec.bits))) dec.bits := i.bits dec.valid := i.valid i.ready := dec.ready |