diff options
| author | Jack Koenig | 2021-01-21 22:50:12 -0800 |
|---|---|---|
| committer | GitHub | 2021-01-21 22:50:12 -0800 |
| commit | dd6871b8b3f2619178c2a333d9d6083805d99e16 (patch) | |
| tree | 825776855e7d2fc28ef32ebb05df7339c24e00b3 /src/main/scala/chisel3/util | |
| parent | 616256c35cb7de8fcd97df56af1986b747abe54d (diff) | |
| parent | 53c24cb0a369d4c4f57c28c098b30e4d3640eac2 (diff) | |
Merge pull request #1745 from chipsalliance/remove-val-io
Remove "val io" and rename MultiIOModule to Module
Diffstat (limited to 'src/main/scala/chisel3/util')
| -rw-r--r-- | src/main/scala/chisel3/util/Decoupled.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index c6459455..032d731d 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -21,7 +21,7 @@ abstract class ReadyValidIO[+T <: Data](gen: T) extends Bundle { // Compatibility hack for rocket-chip private val genType = (DataMirror.internal.isSynthesizable(gen), chisel3.internal.Builder.currentModule) match { - case (true, Some(module: MultiIOModule)) + case (true, Some(module: Module)) if !module.compileOptions.declaredTypeMustBeUnbound => chiselTypeOf(gen) case _ => gen } |