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| author | Albert Magyar | 2021-02-01 14:06:39 -0800 |
|---|---|---|
| committer | GitHub | 2021-02-01 22:06:39 +0000 |
| commit | 98ce9194e5d87fdd5be931b6cd516d180a6540cd (patch) | |
| tree | babdfd24728a20188a170839d05d03b30aa11685 /src/main/scala/chisel3/util | |
| parent | 445b5cecb267adcd556627ffea2486b20740d6d4 (diff) | |
Update reported width from div/rem to match FIRRTL results (#1748)
* Update reported width from div/rem to match FIRRTL results
* Add tests for width of % and / on UInt and SInt
* Add loop-based test for known UInt/SInt op result widths
Co-authored-by: Jack Koenig <koenig@sifive.com>
Diffstat (limited to 'src/main/scala/chisel3/util')
0 files changed, 0 insertions, 0 deletions