diff options
| author | Jim Lawson | 2016-09-29 14:57:42 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-09-29 14:57:42 -0700 |
| commit | 96fb6a5e2c781b20470d02eac186b1b129c20bdf (patch) | |
| tree | 242e9c5d1c5e63bb73bb3cb2c11d056a9e3bbcb9 /src/main/scala/chisel3/util | |
| parent | eb5e5dc30019be342b7a0534b425bf33b7984ce3 (diff) | |
Consolidate CompileOptions and re-enable NotStrict pending macro work.
Diffstat (limited to 'src/main/scala/chisel3/util')
| -rw-r--r-- | src/main/scala/chisel3/util/Arbiter.scala | 3 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/Counter.scala | 2 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/Decoupled.scala | 3 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/LFSR.scala | 2 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/Reg.scala | 3 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/Valid.scala | 3 |
6 files changed, 10 insertions, 6 deletions
diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala index adeb1b34..89bb644a 100644 --- a/src/main/scala/chisel3/util/Arbiter.scala +++ b/src/main/scala/chisel3/util/Arbiter.scala @@ -6,7 +6,8 @@ package chisel3.util import chisel3._ -//import chisel3.ExplicitCompileOptions.NotStrict +// TODO: remove this once we have CompileOptions threaded through the macro system. +import chisel3.core.ExplicitCompileOptions.NotStrict /** IO bundle definition for an Arbiter, which takes some number of ready-valid inputs and outputs * (selects) at most one. diff --git a/src/main/scala/chisel3/util/Counter.scala b/src/main/scala/chisel3/util/Counter.scala index b22cfa7b..ba66d667 100644 --- a/src/main/scala/chisel3/util/Counter.scala +++ b/src/main/scala/chisel3/util/Counter.scala @@ -3,7 +3,7 @@ package chisel3.util import chisel3._ -//import chisel3.ExplicitCompileOptions.Strict +//import chisel3.core.ExplicitCompileOptions.Strict /** A counter module * diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index 947d02f8..a0cbf4f7 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -6,7 +6,8 @@ package chisel3.util import chisel3._ -//import chisel3.ExplicitCompileOptions.NotStrict +// TODO: remove this once we have CompileOptions threaded through the macro system. +import chisel3.core.ExplicitCompileOptions.NotStrict /** An I/O Bundle containing 'valid' and 'ready' signals that handshake * the transfer of data stored in the 'bits' subfield. diff --git a/src/main/scala/chisel3/util/LFSR.scala b/src/main/scala/chisel3/util/LFSR.scala index 95b4da81..fedbf194 100644 --- a/src/main/scala/chisel3/util/LFSR.scala +++ b/src/main/scala/chisel3/util/LFSR.scala @@ -6,7 +6,7 @@ package chisel3.util import chisel3._ -//import chisel3.ExplicitCompileOptions.Strict +//import chisel3.core.ExplicitCompileOptions.Strict // scalastyle:off magic.number object LFSR16 { diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala index fcfc9ac5..713a3b2e 100644 --- a/src/main/scala/chisel3/util/Reg.scala +++ b/src/main/scala/chisel3/util/Reg.scala @@ -3,7 +3,8 @@ package chisel3.util import chisel3._ -//import chisel3.ExplicitCompileOptions.NotStrict +// TODO: remove this once we have CompileOptions threaded through the macro system. +import chisel3.core.ExplicitCompileOptions.NotStrict object RegNext { /** Returns a register with the specified next and no reset initialization. diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala index 67be7648..3d153a2a 100644 --- a/src/main/scala/chisel3/util/Valid.scala +++ b/src/main/scala/chisel3/util/Valid.scala @@ -6,7 +6,8 @@ package chisel3.util import chisel3._ -//import chisel3.ExplicitCompileOptions.NotStrict +// TODO: remove this once we have CompileOptions threaded through the macro system. +import chisel3.core.ExplicitCompileOptions.NotStrict /** An Bundle containing data and a signal determining if it is valid */ class Valid[+T <: Data](gen: T) extends Bundle |