Move blackbox verilog implementations within reach of verilator (#453)

* Move blackbox verilog implementations within reach of verilator
Blackbox implementers can annotate the modules with information on where to get the source verilog
This API is very lightweight, real work is done in firrtl in companion PR
Added some verilog to BlackBoxTest.v resource for testing

* if a file named black_box_verilog_files.f exists add a
-f black_box_verilog_files.f to the verilog to cpp command

1 files changed, 24 insertions, 0 deletions

diff --git a/src/main/scala/chisel3/util/BlackBoxUtils.scala b/src/main/scala/chisel3/util/BlackBoxUtils.scala
new file mode 100644
index 00000000..084d58f9
--- /dev/null
+++ b/src/main/scala/chisel3/util/BlackBoxUtils.scala
@@ -0,0 +1,24 @@
+// See LICENSE for license details.
+
+package chisel3.util
+
+import chisel3._
+import chisel3.core.ChiselAnnotation
+import firrtl.transforms.{BlackBoxInline, BlackBoxResource, BlackBoxSourceHelper}
+
+trait HasBlackBoxResource extends BlackBox {
+  self: Module =>
+
+  def setResource(blackBoxResource: String): Unit = {
+    annotate(ChiselAnnotation(self, classOf[BlackBoxSourceHelper], BlackBoxResource(blackBoxResource).serialize))
+  }
+}
+
+trait HasBlackBoxInline extends BlackBox {
+  self: Module =>
+
+  def setInline(blackBoxName: String, blackBoxInline: String): Unit = {
+    annotate(ChiselAnnotation(
+      self, classOf[BlackBoxSourceHelper], BlackBoxInline(blackBoxName, blackBoxInline).serialize))
+  }
+}