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authorJack2022-11-11 06:53:04 +0000
committerJack2022-11-11 06:53:04 +0000
commit3ce953c81f06519351c48277e3474b5720ec07ff (patch)
treeac79dcb80d0528c2ae86ca21da4cf424715ab645 /src/main/scala/chisel3/util
parentadccde9998c91875e5490cff6d5822ffacc593ed (diff)
parentc8046636a25474be4c547c6fe9c6d742ea7b1d13 (diff)
Merge branch '3.5.x' into 3.5-release
Diffstat (limited to 'src/main/scala/chisel3/util')
-rw-r--r--src/main/scala/chisel3/util/Decoupled.scala3
-rw-r--r--src/main/scala/chisel3/util/experimental/ForceNames.scala3
-rw-r--r--src/main/scala/chisel3/util/experimental/decode/decoder.scala2
3 files changed, 5 insertions, 3 deletions
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index b21bd04f..f8c8f9e9 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -7,7 +7,6 @@ package chisel3.util
import chisel3._
import chisel3.experimental.{requireIsChiselType, DataMirror, Direction}
-import chisel3.internal.naming._ // can't use chisel3_ version because of compile order
import scala.annotation.nowarn
@@ -136,7 +135,6 @@ object Decoupled {
*
* @note unsafe (and will error) on the producer (input) side of an IrrevocableIO
*/
- @chiselName
def apply[T <: Data](irr: IrrevocableIO[T]): DecoupledIO[T] = {
require(
DataMirror.directionOf(irr.bits) == Direction.Output,
@@ -403,7 +401,6 @@ object Queue {
* consumer.io.in <> Queue(producer.io.out, 16)
* }}}
*/
- @chiselName
def irrevocable[T <: Data](
enq: ReadyValidIO[T],
entries: Int = 2,
diff --git a/src/main/scala/chisel3/util/experimental/ForceNames.scala b/src/main/scala/chisel3/util/experimental/ForceNames.scala
index 53ee2bd2..3070a210 100644
--- a/src/main/scala/chisel3/util/experimental/ForceNames.scala
+++ b/src/main/scala/chisel3/util/experimental/ForceNames.scala
@@ -3,6 +3,7 @@
package chisel3.util.experimental
import chisel3.experimental.{annotate, ChiselAnnotation, RunFirrtlTransform}
+import chisel3.internal.Builder
import firrtl.Mappers._
import firrtl._
import firrtl.annotations._
@@ -24,6 +25,7 @@ object forceName {
* @param name Name to force to
*/
def apply[T <: chisel3.Element](signal: T, name: String): T = {
+ if (!signal.isSynthesizable) Builder.deprecated(s"Using forceName '$name' on non-hardware value $signal")
annotate(new ChiselAnnotation with RunFirrtlTransform {
def toFirrtl = ForceNameAnnotation(signal.toTarget, name)
override def transformClass: Class[_ <: Transform] = classOf[ForceNamesTransform]
@@ -37,6 +39,7 @@ object forceName {
* @param signal Signal to name
*/
def apply[T <: chisel3.Element](signal: T): T = {
+ if (!signal.isSynthesizable) Builder.deprecated(s"Using forceName on non-hardware value $signal")
annotate(new ChiselAnnotation with RunFirrtlTransform {
def toFirrtl = ForceNameAnnotation(signal.toTarget, signal.toTarget.ref)
override def transformClass: Class[_ <: Transform] = classOf[ForceNamesTransform]
diff --git a/src/main/scala/chisel3/util/experimental/decode/decoder.scala b/src/main/scala/chisel3/util/experimental/decode/decoder.scala
index 4feda672..067dd6f8 100644
--- a/src/main/scala/chisel3/util/experimental/decode/decoder.scala
+++ b/src/main/scala/chisel3/util/experimental/decode/decoder.scala
@@ -6,6 +6,7 @@ import chisel3._
import chisel3.experimental.{annotate, ChiselAnnotation}
import chisel3.util.{pla, BitPat}
import chisel3.util.experimental.{getAnnotations, BitSet}
+import chisel3.internal.Builder
import firrtl.annotations.Annotation
import logger.LazyLogging
@@ -30,6 +31,7 @@ object decoder extends LazyLogging {
val (plaInput, plaOutput) =
pla(minimizedTable.table.toSeq, BitPat(minimizedTable.default.value.U(minimizedTable.default.getWidth.W)))
+ assert(plaOutput.isSynthesizable, s"Using DecodeTableAnnotation on non-hardware value $plaOutput")
annotate(new ChiselAnnotation {
override def toFirrtl: Annotation =
DecodeTableAnnotation(plaOutput.toTarget, truthTable.toString, minimizedTable.toString)