diff options
| author | mergify[bot] | 2021-11-21 05:03:13 +0000 |
|---|---|---|
| committer | GitHub | 2021-11-21 05:03:13 +0000 |
| commit | af7f263941e796b20d65d984bdc4fa3739e2d9b6 (patch) | |
| tree | e0ca1e90bc86ae67e1d55d4d574e95acd7a94210 /src/main/scala/chisel3/util/random | |
| parent | 27b35f49bd1ec178e693a5e5ec33193a80bb1140 (diff) | |
| parent | 8f796df5693b560a086b95a24c5bd090064a639e (diff) | |
Merge branch 'master' into update/sbt-scoverage-1.9.2
Diffstat (limited to 'src/main/scala/chisel3/util/random')
| -rw-r--r-- | src/main/scala/chisel3/util/random/PRNG.scala | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/src/main/scala/chisel3/util/random/PRNG.scala b/src/main/scala/chisel3/util/random/PRNG.scala index 9b42acf1..3a44385a 100644 --- a/src/main/scala/chisel3/util/random/PRNG.scala +++ b/src/main/scala/chisel3/util/random/PRNG.scala @@ -7,16 +7,23 @@ import chisel3.util.Valid /** Pseudo Random Number Generators (PRNG) interface * @param n the width of the LFSR + * @groupdesc Signals The actual hardware fields of the Bundle */ class PRNGIO(val n: Int) extends Bundle { - /** A [[chisel3.util.Valid Valid]] interface that can be used to set the seed (internal PRNG state) */ + /** A [[chisel3.util.Valid Valid]] interface that can be used to set the seed (internal PRNG state) + * @group Signals + */ val seed: Valid[Vec[Bool]] = Input(Valid(Vec(n, Bool()))) - /** When asserted, the PRNG will increment by one */ + /** When asserted, the PRNG will increment by one + * @group Signals + */ val increment: Bool = Input(Bool()) - /** The current state of the PRNG */ + /** The current state of the PRNG + * @group Signals + */ val out: Vec[Bool] = Output(Vec(n, Bool())) } |
