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| author | Abongwa Bonalais | 2021-11-03 05:56:37 +0100 |
|---|---|---|
| committer | GitHub | 2021-11-03 04:56:37 +0000 |
| commit | a79f57565e7157d137628d1aaeae750f98e3d88b (patch) | |
| tree | 2f3289ae48c50b5ba1fe36297caae44b22d53ce7 /src/main/scala/chisel3/util/random | |
| parent | cdf130f32895f4fedd49f742d49b17c2baa791ac (diff) | |
Add field grouping ScalaDoc for other subclasses of Bundle (#2214)
* Add field grouping scaladocs for DecoupledIo
* Added groupdesc to DecoupledIO
* Added groupings for IrrevocableIO
* Add groupings for ValidIO
* Add field grouping scaladoc for PRNGIO
* Add field grouping scaladoc for QueueIO
* Added groupings for PipeIO
* Update src/main/scala/chisel3/util/Decoupled.scala
Commited Sugestion
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update src/main/scala/chisel3/util/Decoupled.scala
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update src/main/scala/chisel3/util/Decoupled.scala
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update src/main/scala/chisel3/util/Decoupled.scala
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update src/main/scala/chisel3/util/Decoupled.scala
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update src/main/scala/chisel3/util/Valid.scala
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update src/main/scala/chisel3/util/Valid.scala
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update src/main/scala/chisel3/util/Valid.scala
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Megan Wachs <megan@sifive.com>
Diffstat (limited to 'src/main/scala/chisel3/util/random')
| -rw-r--r-- | src/main/scala/chisel3/util/random/PRNG.scala | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/src/main/scala/chisel3/util/random/PRNG.scala b/src/main/scala/chisel3/util/random/PRNG.scala index 9b42acf1..3a44385a 100644 --- a/src/main/scala/chisel3/util/random/PRNG.scala +++ b/src/main/scala/chisel3/util/random/PRNG.scala @@ -7,16 +7,23 @@ import chisel3.util.Valid /** Pseudo Random Number Generators (PRNG) interface * @param n the width of the LFSR + * @groupdesc Signals The actual hardware fields of the Bundle */ class PRNGIO(val n: Int) extends Bundle { - /** A [[chisel3.util.Valid Valid]] interface that can be used to set the seed (internal PRNG state) */ + /** A [[chisel3.util.Valid Valid]] interface that can be used to set the seed (internal PRNG state) + * @group Signals + */ val seed: Valid[Vec[Bool]] = Input(Valid(Vec(n, Bool()))) - /** When asserted, the PRNG will increment by one */ + /** When asserted, the PRNG will increment by one + * @group Signals + */ val increment: Bool = Input(Bool()) - /** The current state of the PRNG */ + /** The current state of the PRNG + * @group Signals + */ val out: Vec[Bool] = Output(Vec(n, Bool())) } |