diff options
| author | mergify[bot] | 2021-11-21 05:45:01 +0000 |
|---|---|---|
| committer | GitHub | 2021-11-21 05:45:01 +0000 |
| commit | 7adc8063570994dc87a9bfe151b6800d45e26bbc (patch) | |
| tree | a69854ddb53c1b6540d78e3eb2b50d589168ccfe /src/main/scala/chisel3/util/random | |
| parent | aadd08e1e88947b615749be139ce36f4fbbbedf0 (diff) | |
| parent | 0a8bc71dde53f45672eb249454262a6a31c27e93 (diff) | |
Merge branch 'master' into update/sbt-mdoc-2.2.24
Diffstat (limited to 'src/main/scala/chisel3/util/random')
| -rw-r--r-- | src/main/scala/chisel3/util/random/PRNG.scala | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/src/main/scala/chisel3/util/random/PRNG.scala b/src/main/scala/chisel3/util/random/PRNG.scala index 9b42acf1..3a44385a 100644 --- a/src/main/scala/chisel3/util/random/PRNG.scala +++ b/src/main/scala/chisel3/util/random/PRNG.scala @@ -7,16 +7,23 @@ import chisel3.util.Valid /** Pseudo Random Number Generators (PRNG) interface * @param n the width of the LFSR + * @groupdesc Signals The actual hardware fields of the Bundle */ class PRNGIO(val n: Int) extends Bundle { - /** A [[chisel3.util.Valid Valid]] interface that can be used to set the seed (internal PRNG state) */ + /** A [[chisel3.util.Valid Valid]] interface that can be used to set the seed (internal PRNG state) + * @group Signals + */ val seed: Valid[Vec[Bool]] = Input(Valid(Vec(n, Bool()))) - /** When asserted, the PRNG will increment by one */ + /** When asserted, the PRNG will increment by one + * @group Signals + */ val increment: Bool = Input(Bool()) - /** The current state of the PRNG */ + /** The current state of the PRNG + * @group Signals + */ val out: Vec[Bool] = Output(Vec(n, Bool())) } |
