Avoid when(reset) construct in LFSR

Muxes and resets are only isomorphic with synchronous reset.  Use a reset
instead of a conditional to make this async-reset-safe.

1 files changed, 7 insertions, 4 deletions

diff --git a/src/main/scala/chisel3/util/random/PRNG.scala b/src/main/scala/chisel3/util/random/PRNG.scala
index c74759b0..37f50599 100644
--- a/src/main/scala/chisel3/util/random/PRNG.scala
+++ b/src/main/scala/chisel3/util/random/PRNG.scala
@@ -33,15 +33,18 @@ abstract class PRNG(val width: Int, val seed: Option[BigInt], step: Int = 1, upd
 
   val io: PRNGIO = IO(new PRNGIO(width))
 
+  /** Allow implementations to override the reset value, e.g., if some bits should be don't-cares. */
+  protected def resetValue: Vec[Bool] = seed match {
+    case Some(s) => VecInit(s.U(width.W).asBools)
+    case None    => WireDefault(Vec(width, Bool()), DontCare)
+  }
+
   /** Internal state of the PRNG. If the user sets a seed, this is initialized to the seed. If the user does not set a
     * seed this is left uninitialized. In the latter case, a PRNG subclass *must do something to handle lockup*, e.g.,
     * the PRNG state should be manually reset to a safe value. [[LFSR]] handles this by, based on the chosen reduction
     * operator, either sets or resets the least significant bit of the state.
     */
-  private [random] val state: Vec[Bool] = seed match {
-    case Some(s) => RegInit(VecInit(s.U(width.W).asBools))
-    case None    => Reg(Vec(width, Bool()))
-  }
+  private [random] val state: Vec[Bool] = RegInit(resetValue)
 
   /** State update function
     * @param s input state