diff options
| author | Jiuyang Liu | 2021-12-15 15:53:52 +0800 |
|---|---|---|
| committer | GitHub | 2021-12-15 07:53:52 +0000 |
| commit | 36506c527ff0f51636beee4160f0ce1f6ad2f90a (patch) | |
| tree | ef6f708959d6f115154d76ddd6216a7ba288a01f /src/main/scala/chisel3/util/experimental/decode/decoder.scala | |
| parent | 7e8ec50376f852d5ab35d7609d986c7e4128abb1 (diff) | |
Refactor TruthTable to use Seq (#2217)
This makes the resulting Verilog from decoding a TruthTable deterministic.
Diffstat (limited to 'src/main/scala/chisel3/util/experimental/decode/decoder.scala')
| -rw-r--r-- | src/main/scala/chisel3/util/experimental/decode/decoder.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/util/experimental/decode/decoder.scala b/src/main/scala/chisel3/util/experimental/decode/decoder.scala index 42e374d1..ee2ece48 100644 --- a/src/main/scala/chisel3/util/experimental/decode/decoder.scala +++ b/src/main/scala/chisel3/util/experimental/decode/decoder.scala @@ -19,7 +19,7 @@ object decoder extends LazyLogging { */ def apply(minimizer: Minimizer, input: UInt, truthTable: TruthTable): UInt = { val minimizedTable = getAnnotations().collect { - case DecodeTableAnnotation(_, in, out) => TruthTable(in) -> TruthTable(out) + case DecodeTableAnnotation(_, in, out) => TruthTable.fromString(in) -> TruthTable.fromString(out) }.toMap.getOrElse(truthTable, minimizer.minimize(truthTable)) if (minimizedTable.table.isEmpty) { val outputs = Wire(UInt(minimizedTable.default.getWidth.W)) |