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authorAlbert Magyar2020-07-21 17:40:16 -0700
committerGitHub2020-07-21 17:40:16 -0700
commit473a13877c60ba9fb13de47542a8397412c2b967 (patch)
tree159cec6aa6ece2e87ceffbdc56a553fe71d0726b /src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
parent4a0e828cfe76e0d3bd6c4a0cc593589fe74ed0ba (diff)
parente5568f55a6a149adfd19ad04b264a69078288f86 (diff)
Merge pull request #1519 from freechipsproject/no-scalastyle
Remove scalastyle configurations
Diffstat (limited to 'src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala')
-rw-r--r--src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala b/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
index 3d14b5c2..92bfcde7 100644
--- a/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
+++ b/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
@@ -123,7 +123,6 @@ object loadMemoryFromFile {
* Currently the only non-Verilog based simulation that can support loading memory from a file is treadle but it does
* not need this transform to do that.
*/
-//scalastyle:off method.length
class LoadMemoryTransform extends Transform {
def inputForm: CircuitForm = LowForm
def outputForm: CircuitForm = LowForm