diff options
| author | Aditya Naik | 2024-08-06 07:51:25 -0700 |
|---|---|---|
| committer | Aditya Naik | 2024-08-06 07:51:25 -0700 |
| commit | 315923aa09101f6c6ffc58a445bd7411b3b23fca (patch) | |
| tree | b8533ceaf9b291a718a4b7f505cf5d4b1f0e7803 /src/main/scala/chisel3/util/experimental/BoringUtils.scala | |
| parent | 276d7261208d640ea57a48cb592775c677726fb0 (diff) | |
Fix more misc fileschisel6-scala3-0.1
Diffstat (limited to 'src/main/scala/chisel3/util/experimental/BoringUtils.scala')
| -rw-r--r-- | src/main/scala/chisel3/util/experimental/BoringUtils.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/util/experimental/BoringUtils.scala b/src/main/scala/chisel3/util/experimental/BoringUtils.scala index 254f83a4..0bbe000d 100644 --- a/src/main/scala/chisel3/util/experimental/BoringUtils.scala +++ b/src/main/scala/chisel3/util/experimental/BoringUtils.scala @@ -4,7 +4,7 @@ package chisel3.util.experimental import chisel3._ import chisel3.experimental.{annotate, ChiselAnnotation, RunFirrtlTransform} -import chisel3.internal.{InstanceId, NamedComponent, Namespace} +import chisel3.internal.{NamedComponent, Namespace} import firrtl.transforms.{DontTouchAnnotation, NoDedupAnnotation} import firrtl.passes.wiring.{SinkAnnotation, SourceAnnotation, WiringTransform} import firrtl.annotations.{ComponentName, ModuleName} |