diff options
| author | mergify[bot] | 2022-06-27 16:38:41 +0000 |
|---|---|---|
| committer | GitHub | 2022-06-27 16:38:41 +0000 |
| commit | 3063a1b853726e0bc65d7211ea2e584275774412 (patch) | |
| tree | 88e600ad00c05a6b82f198f7b82e39423b672dd2 /src/main/scala/chisel3/util/Valid.scala | |
| parent | 7fc023cd2983cc22a309636d3cd7e0d9066cd805 (diff) | |
Deprecate TransitName (backport #2603) (#2606)
* Deprecate TransitName (#2603)
* Deprecate TransitName
* Add @nowarn macros to usages of TransitName in the repo
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit a0b05190e5303ec28a0c7abe645d81e9a72023ff)
* Update src/main/scala/chisel3/util/Valid.scala
* Update src/main/scala/chisel3/util/Valid.scala
Co-authored-by: Megan Wachs <megan@sifive.com>
Diffstat (limited to 'src/main/scala/chisel3/util/Valid.scala')
| -rw-r--r-- | src/main/scala/chisel3/util/Valid.scala | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala index eeb2ab68..cb0e166a 100644 --- a/src/main/scala/chisel3/util/Valid.scala +++ b/src/main/scala/chisel3/util/Valid.scala @@ -7,6 +7,8 @@ package chisel3.util import chisel3._ +import scala.annotation.nowarn + /** A [[Bundle]] that adds a `valid` bit to some data. This indicates that the user expects a "valid" interface between * a producer and a consumer. Here, the producer asserts the `valid` bit when data on the `bits` line contains valid * data. This differs from [[DecoupledIO]] or [[IrrevocableIO]] as there is no `ready` line that the consumer can use @@ -116,6 +118,7 @@ object Pipe { * @param latency the number of pipeline stages * @return $returnType */ + @nowarn("cat=deprecation&msg=TransitName") def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int)(implicit compileOptions: CompileOptions): Valid[T] = { require(latency >= 0, "Pipe latency must be greater than or equal to zero!") if (latency == 0) { |