diff options
| author | Jim Lawson | 2017-05-25 09:03:25 -0700 |
|---|---|---|
| committer | GitHub | 2017-05-25 09:03:25 -0700 |
| commit | 0d121a2e357511e9e7d975ae5f2d316e47cbf43b (patch) | |
| tree | 533691f828b87eb4e700400d7ec88c4d0b5bfd81 /src/main/scala/chisel3/util/Valid.scala | |
| parent | cb28230d50475428f432b2906dd5246e27f3a687 (diff) | |
Update internal Pipe wiring - fixes #615" (#616)
Replace ambiguous bi-connect ("<>") with mono-connect (":=") for internal Pipe wiring.
Diffstat (limited to 'src/main/scala/chisel3/util/Valid.scala')
| -rw-r--r-- | src/main/scala/chisel3/util/Valid.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala index f95bb17c..6fb67585 100644 --- a/src/main/scala/chisel3/util/Valid.scala +++ b/src/main/scala/chisel3/util/Valid.scala @@ -38,8 +38,8 @@ object Pipe def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int)(implicit compileOptions: CompileOptions): Valid[T] = { if (latency == 0) { val out = Wire(Valid(enqBits)) - out.valid <> enqValid - out.bits <> enqBits + out.valid := enqValid + out.bits := enqBits out } else { val v = RegNext(enqValid, false.B) |