diff options
| author | ducky | 2016-09-22 15:21:48 -0700 |
|---|---|---|
| committer | ducky | 2016-09-22 15:21:48 -0700 |
| commit | decb2ee0f0bb8223f0b2b067b88ed90b71473a28 (patch) | |
| tree | 459cd428fd78b2f5d15aa1e841c15f1ba17af154 /src/main/scala/chisel3/util/LFSR.scala | |
| parent | 6eb00023fcc3ad77b98e51971f6e193ea506b9cc (diff) | |
Update rest of docs
Diffstat (limited to 'src/main/scala/chisel3/util/LFSR.scala')
| -rw-r--r-- | src/main/scala/chisel3/util/LFSR.scala | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/src/main/scala/chisel3/util/LFSR.scala b/src/main/scala/chisel3/util/LFSR.scala index a30c276f..e4261c20 100644 --- a/src/main/scala/chisel3/util/LFSR.scala +++ b/src/main/scala/chisel3/util/LFSR.scala @@ -8,12 +8,13 @@ package chisel3.util import chisel3._ // scalastyle:off magic.number -/** linear feedback shift register - */ -object LFSR16 -{ - def apply(increment: Bool = Bool(true)): UInt = - { +object LFSR16 { + /** Generates a 16-bit linear feedback shift register, returning the register contents. + * May be useful for generating a pseudorandom sequence. + * + * @param increment optional control to gate when the LFSR updates. + */ + def apply(increment: Bool = Bool(true)): UInt = { val width = 16 val lfsr = Reg(init=UInt(1, width)) when (increment) { lfsr := Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)) } |
