diff options
| author | Jim Lawson | 2016-12-02 12:51:03 -0800 |
|---|---|---|
| committer | GitHub | 2016-12-02 12:51:03 -0800 |
| commit | d3ec37edd39799e8cf039e5caed915c00dff7eeb (patch) | |
| tree | 03329ddc11ca15b9d6c7f832354a9cba20c87843 /src/main/scala/chisel3/util/LFSR.scala | |
| parent | 1b53d893816d349f5ea18fa0ed13325b9f1b6917 (diff) | |
| parent | eba224e524b249207b47a3b378458c61c9b66e2c (diff) | |
Merge branch 'master' into exceptionfix
Diffstat (limited to 'src/main/scala/chisel3/util/LFSR.scala')
| -rw-r--r-- | src/main/scala/chisel3/util/LFSR.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/util/LFSR.scala b/src/main/scala/chisel3/util/LFSR.scala index fedbf194..83dc907d 100644 --- a/src/main/scala/chisel3/util/LFSR.scala +++ b/src/main/scala/chisel3/util/LFSR.scala @@ -15,9 +15,9 @@ object LFSR16 { * * @param increment optional control to gate when the LFSR updates. */ - def apply(increment: Bool = Bool(true)): UInt = { + def apply(increment: Bool = true.B): UInt = { val width = 16 - val lfsr = Reg(init=UInt(1, width)) + val lfsr = Reg(init=1.U(width.W)) when (increment) { lfsr := Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)) } lfsr } |
